Say we have this cmos circuit any advice how you would size up the transistors assuming that the gate is minimum-sized. Ive done some reading and I am struggling to understand. Is there an definition to define this?? I feel like it is really simple. Thanks
For minimum sizing, we usually say that L is minimal. What we actually scale is the W.
The NMOS in a inverter of minimal size is defined as being of size "1". All other sizes are in reference to this.
Depending on the coursebook you ask, a PMOS is said to be "2 times worse" than a NMOS of the same size. So our default inverter looks like this (I used to more common transistor symbol found in most digital/VLSI design textbooks):
What we usually want, is that when the output is pulled to 0 by a certain set of inputs, the resistance to ground (or rather, the current capability of the gate) is the same as that of a single inverter. This means, if you have 2 transistors in series to ground, you need to make them 2 times bigger to compensate.
I've redrawn the pulldown network from the gate in your question.
When we look at this, we can see that E gives us a path from the output to ground. Therefor, we can keep this minimal, and it's size will be 1.
C', D', A and B form parallel/series branches. In the worst case (worst case where we still have a output equal to 0, ofcourse), only one transistor of each parallel pair will be on. So, we will have 2 gates in series. This doubles their resistance, so we need to also double their size to compensate. In other words, these transistors will be size 2.