How should BMI160 registers be set to enable detection flags to be set in INT_STATUS?

For example, how to get TAP_STATUS byte-0 bit-5 s_tap_int to set if XDK110 is tapped?

I don't need actual interrupt, I just want a poll loop to periodically read flags in INT_STATUS to check for detection of the various motion events (tap, shock, etc.)


I've enabled this on 2 embedded systems. In order to enable the tap interrupt (or any interrupt for that matter), you simply need to set the enable bit to 1. If you want to map it to an interrupt output... say INT1... you then need to map it to the INT1 pin:

#define BMI160_REG_INT_EN_0    0x50
#define INT_S_TAP_EN           (1<<5)

#define BMI160_REG_INT_MAP_0   0x55
#define INT1_S_TAP             (1<<5)

bmi_write(BMI160_REG_INT_EN_0, INT_S_TAP_EN);
bmi_write(BMI160_REG_INT_MAP_0, INT1_S_TAP);

Also, if you do want this interrupt to truly latch (stay true forever), you can enable latching by setting register 0x54 = 0x0F. I believe the interrupts can be cleared by setting this register to 0, then back to 0x0F. It may also be preferable to set the latch time to 2x your polling rate so that you can catch it. The equation seems to be:

t = 312.5us x 2^([bits 3:0] - 1)

Thus setting bits 3:0 = 0x4 gives you: 312.5us x 2 (4-1) = 312.5us * 8 = 2.5ms

Some traps I've fallen into with the BMI involve not setting the correct power modes ahead of time and not adding a delay between writes (450us for fully suspended system, 3us for normal & low power modes).

For reference, I have my accelerometer set as follows: low-power mode, 25Hz ODR, under sampling enabled, BWP set to normal.

#define BMI160_REG_CMD          0x7E
#define CMD_PMU_ACC_LPW         (0x12)

#define BMI160_REG_ACC_RANGE    0x41
#define ACC_RANGE_4G            (5<<0)

#define BMI160_REG_ACC_CONF     0x40
#define ACC_US                  (1<<7)
#define ACC_BWP_NORM            (2<<4)
#define ACC_ODR_25              (6<<0)

bmi_write(BMI160_REG_CMD, CMD_PMU_ACC_LPW);
bmi_write(BMI160_REG_ACC_RANGE, ACC_RANGE_4G);
bmi_write(BMI160_REG_ACC_CONF, ACC_US | ACC_BWP_NORM | ACC_ODR_25 );

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