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I'm having major problems making a good layout with a through hole USB-C connector. Have anyone done a good layout for one? The best I have managed now looks pretty terrible and one of the differential traces has 5 vias, which is not recommended.

I'm using the spraar7f manual from Texas Instruments for spacings, linewidths etc. I have never done anything USB3 or USB-C, only 2.0 and I'd be really happy with some guidence. Will this implementation be OK? I have tried routing it some different ways, this is at least symetrical. Everything is length-matched according to spec.

Image of USB-C: Image of USB-C Image of trace with 5 vias: Image of trace with 5 vias

I have chosen a through hole connector to make it easier to solder and for robustness, but I'm currently thinking of replacing it for a completely surface mount one. Currently I'm designing for a Wurth 632723300011 (there are other brands with the same footprint)

It's a 4-layer PCV

Any ideas? :)

EDIT: As noticed out by asdfex, there is an error in the footprint. Do not follow the answer in this thread. It will give an incorrect layout. (Thanks for noticing!)

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  • \$\begingroup\$ Is this a 2 layer board ? I doubt you can route this on 2 layers \$\endgroup\$ – Mike Apr 12 '17 at 15:44
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    \$\begingroup\$ Did you use an autorouter to route this? It looks to me that there are several unnecessary vias/layer changes in those tracks. A little manual routing could remove at least 8 vias. \$\endgroup\$ – Peter Bennett Apr 12 '17 at 15:51
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    \$\begingroup\$ Put your effort first into routing the high speed pairs, then the d+/d-, then everything else. Also do you have a datasheet for the connector? Seems an odd footprint. A screenshot of the connector portion of the schematic would also help. \$\endgroup\$ – Tom Carpenter Apr 12 '17 at 16:14
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    \$\begingroup\$ I wouldn't have tagged this as an Altium question. \$\endgroup\$ – Joel Wigton Apr 13 '17 at 16:32
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    \$\begingroup\$ Attention: You got the footprint wrong! A11 and B2 are not the same signal! A11 and B11 are. \$\endgroup\$ – asdfex Apr 15 '17 at 11:44
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Based on my suggestion of starting with the SS traces, then the USB D+/-, then whatever is left, this is what I would suggest you do:

Escape Routed

This has completely eliminated all vias on the SS traces near to the connector. You will need a pair of vias on each to drop through to the red layer, however the traces are at least now in the correct order - they no longer need to cross over each other to get to your IC. In terms of length matching, you can no add some meandering further away from the connector where there is space. I would also be tempted to put your TVS diodes on the blue layer.

The only down side here is that the N's and P's need to be crossed over. This can be done as you go through the board by having the trace fold back on itself (the traces leave the pair of vias in the same direction on top and bottom of the board).

Next up comes the USB 2.0. Given that this is relatively low speed in the grand scheme of things, connecting them as shown shouldn't cause too much issue. The way you had routed it is so far from converging that it's probably meaningless to try and route them differentially over the last millimetre. You could of course place your vias further away from the connector, and then route differentially out of the via and round, but I don't think it would make much difference.

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  • \$\begingroup\$ Yes, this looks like the best way to do it. Thanks alot! :) \$\endgroup\$ – Applet Apr 13 '17 at 6:11
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Just by looking quickly at your traces and vias, I have found 4 vias that are unnecessary. Here they are:

enter image description here

You are switching between bottom and top layer twice instead of staying on the top layer.

Furthermore, if you are putting vias to go from one layer to another, make sure the bottom traces are as short as possible to reduce space. For example, you have abnormal length of traces for UP_SS_TX_P and UP_SS_TX_N. You can put the vias right by the traces you are trying to jump under.

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  • \$\begingroup\$ Thanks for the responce! The reason for the layer switch is to invert the order of UP_SS_TX_P and UP_SS_TX_N, so I can't stay on the top layer (red). So they are not unneccesary. I will upload a pic \$\endgroup\$ – Applet Apr 12 '17 at 16:02
  • \$\begingroup\$ Also, with more vias comes more inductance. \$\endgroup\$ – ammar.cma Apr 12 '17 at 16:03
  • \$\begingroup\$ The reason for the vias on the SSRX and SSTX is to switch the order of the P and N-traces in order to be able to connect them with the SMD-pads of the connector. See image below, hopefully it explains it. Image: i.stack.imgur.com/glPOx.png \$\endgroup\$ – Applet Apr 12 '17 at 16:14
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    \$\begingroup\$ @Applet You can switch the blue traces with each other, and still invert the order without those extra four vias. And you can do the same on the other side. \$\endgroup\$ – uint128_t Apr 12 '17 at 16:18
  • \$\begingroup\$ @uint128_t Yes, that is true, I have in total 4 extra vias, 2 per differential pairs. The reason for this is that i read in the spraar7f from TI that I should try to have the eaqual number of vias on each differential pair trace (page 14). Or am I still missing something? \$\endgroup\$ – Applet Apr 12 '17 at 16:21
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So, as you correctly pointed out, there were som unnessesary vias. I revised it to look like this: (which is much better) fewer vias! Now I'm down to 3 vias on the SSTX trace, which is closer to the maximum of 2 vias at least. I'm a bit concerned about the length matching i Altium, will it calculate correctly when I don't place the vias symetrically?

Thanks for the help so far, trying to learn here :)

Total trace: total trace

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    \$\begingroup\$ There is a possibily neater still way of doing it. When I'm back at a computer rather than phone I'll draw a sketch. \$\endgroup\$ – Tom Carpenter Apr 12 '17 at 19:37
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Those are pretty long stubs to be carrying USB 3.0 traffic by. Have you thought about using a USB-C SuperSpeed mux? They would make routing substantially easier.

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  • \$\begingroup\$ I did not think about that option, thanks for the tip! I did a quick test-implementation of the TI HD3SS3220-chip, and it really simplifies it a lot. I will update the mail-post when I have a more finished implementation. \$\endgroup\$ – Applet Jul 12 '17 at 8:26

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