I've just started using SPI on a dsPIC, and I noticed some strange behavior on a waveform (see image below). SPI module is configured in the master 8-bit mode. On the shown waveform you can see a byte
0xAB, and that the SPI module "prepares" the data line one clock cycle before the first clock pulse. Why is that? If I send
0x7B (first bit of this byte is
0), then the data line stays low before the first clock pulse. If I send
0xAB just after the first byte, everything is fine, i.e., there is no one dummy clock cycle between the two bytes just "to prepare" for
The SPI mode is as follows: idle state is high, active state is low (CKP=1); serial data changes on transition from idle to active state (CKE=0).