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To measure a lot of (high resistance) resistors in an harsh environment, I want to setup a matrix of these resistors under test (\$R_{00} \dots R_{nm}\$).

The resistors \$R_{x0} \dots R_{xn}\$ and \$R_{y0} \dots R_{ym}\$ are switches to select the resistor under test. These switches have no infinite isolation resistance when open, so I drew them as resistors. An ammeter combined with a voltage source is connected between + and GND.

I want to calculate the error, the rest of the resistor matrix is causing, when activating one resistor.

For example if the switches \$R_{y0}\$ and \$R_{x0}\$ are closed (set to \$0\ \Omega\$) and the other switches are open (set to \$10\ G\Omega\$) to measure the current through \$R_{00}\$, I have to consider the other resistors as a parallel resistance, causing an error for the measurement. How do I calculate this resistance?

When all resistors under test are considered to be equal, and all open switches are considered to be equal, I feel like there has to be some simplification like considering all rows to be connected to each other and the columns to be connected to each other? But I am somehow stuck at proving this and have no real approach.

Resistor measurement matrix

Update:

Like Neil_UK suggested, the following would be a better setup to allow guarding out the current that would go through the rows not having the resistor currently measured. Supposing, the guarding works perfect, the error could be calculated as an parallel resistance of all the isolation resistances \$R_{xn}\$ plus all resistors in the measured row \$R_{xn}\$.

schematic

simulate this circuit – Schematic created using CircuitLab

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You can do better than tolerating that the rest of the resistor matrix causes an error to the one you have selected. You can measure each individually, with minimal error from the others. The technique is called 'guarding'.

Let's say you want to measure resistor Rnm, in row n, column m. Force row n to (say) 1v. Measure the current coming out of column m with a virtual ground transimpedance amplifier (TIA). Measuring the current into a virtual ground input ensures that column m is at 0v, and there is exactly 1v across the resistor. Calculate the resistance as applied voltage / current.

If this was all you did, the other resistors in the matrix would be contributing to a current flow into column m as well.

But we can guard out that current. Force all other rows to 0v. Resistors Rxm now have zero volts across them. As column m is also at 0v, no current flows through them. There is therefore no error in the current measured by column m's TIA.

Resistors Rnx will be conducting current from row n. However, we are forcing that voltage to 1v, not measuring the current flowing through it, so this extra current causes no error in the measurement.

I've said there's minimal error caused by the conduction of the other resistors. If the virtual ground amplifier doesn't hold column m at exactly 0v, or the guarding switches don't drive the other rows to exactly 0v, there will be a voltage across the resistors Rxm. The lower the input offset on the TIA, the lower the switch resistances, the less error the other resistances will cause.

This may appear to use more hardware than simply multiplexing the resistors as you've shown, but not much. Each row requires a 2:1 switch, to connect it to 1v or 0v. All columns can be multiplexed by a single m:1 mux into a single TIA. The TIA is needed anyway to measure the resistance, however you multiplex the resistors.

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  • \$\begingroup\$ Thank you for the excellent hint to improve the setup. Did I understand it correctly? (see update in the question). \$\endgroup\$ – Pascal Rosin Apr 18 '17 at 9:25
  • \$\begingroup\$ Yes, that looks OK. If we are talking about picoamps, then there may be a benefit in attempting to control leakage at the output multiplexer as well, perhaps by making RL4-6 as c/o types as well that switch to ground to divert leakage away from the meter? I'm not sure I understand your 'error calculation', I think you might have swapped indices. However, at the pA/100v level, leakage across relays is not necessarily going to look like a large 'off' resistance, so it probably needs an explicit evaluation and summing of leakage paths in each configuration. \$\endgroup\$ – Neil_UK Apr 18 '17 at 10:08

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