In MIPS, an I type instruction has the following format.

  1. bits [31, 26] are for opcode
  2. bits [25, 21] are for source register
  3. bits [20, 16] are for transfer register
  4. bits [15, 0] are for immediates

If the number of registers used is halved, then I will have two extra bits to use for the immediates. And if I'm assuming 2's complement form, then, I have 18 bits. So is my minimum value for the immediate \$-131072\$ and max value \$131071\$?

  • \$\begingroup\$ How are you removing 2 registers from the cpu? I'm guessing that would take a newly rebuilt cpu, which then could be built to accept 18-bit immediates in an I-type instruction? \$\endgroup\$ – Robherc KV5ROB Apr 12 '17 at 18:55
  • \$\begingroup\$ Also, you'd want to rearrange the bits in your theoretical cpu, because coding an immediate using bits 21 & 60-1 would be rather sloppy. \$\endgroup\$ – Robherc KV5ROB Apr 12 '17 at 19:01
  • \$\begingroup\$ I'm actually removing half the registers. And this is just theoretically speaking. Not for actual implementation. \$\endgroup\$ – Jonathan Apr 12 '17 at 20:59
  • \$\begingroup\$ Yes, I noticed my error on the -2 instead of 1/2 about 20 seconds after the 5 minute edit-timer for my comment expired (not to mention typing '60' instead of '16' in the second comment). :S \$\endgroup\$ – Robherc KV5ROB Apr 12 '17 at 21:06

Assuming all necessary uC architecture adjustments have been made, then you would have an unsigned range of 0-262144, or a signed range of (-)131072-131071.
Your math is correct.


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