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I have the following logic gates.

enter image description here

To figure out what logic function is implemented, I try to develop the truth table.

A | B | out (I guess, not sure)
--|---|--------
1 | 1 |    1
1 | 0 |    ?
0 | 1 |    ?
0 | 0 |    1

I feel like when A=1 and B=1 thenout=1. Also, when A=0 and B=0 then `out=1'. However, I'm not sure about other cases. I wonder if anybody can help.


UPDATE:

When A=1 and B=0 (or when A=0 and B=1), then the output of each block of logic gates might be as shown below.

enter image description here

Therefore the truth table might be like this:

A | B | out (I guess, not sure)
--|---|--------
1 | 1 |    1
1 | 0 |    0
0 | 1 |    0
0 | 0 |    1

If my calculations are correct, the logic gates are implementing something like NXOR (or XNOR?). I'm not sure.

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    \$\begingroup\$ What do you think it is? Try to redraw the diagram and cancel out the mosfets that you know what value they produce. You know the top only can output LOWs and the bottom HIGHs, so what happens if both? Btw I think what you're dealing here is a latch, so a logic table may not suffice by itself unless that's actually the question. \$\endgroup\$ – Bradman175 Apr 13 '17 at 10:25
  • \$\begingroup\$ @Bradman175 Thanks, I feel like out for the other two cases would be 0 \$\endgroup\$ – user4838962 Apr 13 '17 at 10:29
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    \$\begingroup\$ Justify. Not allowed to say whether you're right or wrong. \$\endgroup\$ – Bradman175 Apr 13 '17 at 10:30
  • \$\begingroup\$ I think you need to add out on the previous state to truth table, because out(n) on the next state also will depend on the out(n-1) \$\endgroup\$ – Roman Apr 14 '17 at 4:08
  • \$\begingroup\$ It's really not XNOR because XNOR gate hasn't feedback rather than in your draw \$\endgroup\$ – Roman Apr 14 '17 at 5:33
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I don't know which element exactly has drawn on the picture, but my truth table looks like:

A | B | OUT(n-1) |    OUT(n)
--|---|----------|--------
0 | 0 |   0      |    1
0 | 0 |   1      |    1
0 | 1 |   0      |    0
0 | 1 |   1      |    X
1 | 0 |   0      |    0
1 | 0 |   1      |    X
1 | 1 |   0      |    1
1 | 1 |   1      |    1

But even this truth table I'm not sure that valid, because out doesn't keep it value and A and B can affect to OUT even when Vdd transistor (pMOS) is close .

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