# Resistive on-die termination

It is widely known that resistive termination (e.g. 50 Ohm to ground) is superior when noise is no concern. Specifically in the block diagrams of RFICs I see many 50 Ohm resistors to ground directly driving a CMOS inverter buffer, when used as clock or LO pins.

This works obviously nice in the absence of parasitics but as soon as the bondwire and pad capacitances come into play, the concept of resistive termination fails for me. Consider the following example:

simulate this circuit – Schematic created using CircuitLab

where the source resistance (50 Ohm) is fixed, Cpcb models the PCB pin, L the bondwire, Cpad the bonding pad on the die and Rt denotes a resistor to be chosen freely.

Not only is the optimum value NOT 50 Ohm but around 30 Ohm, also the best possible S11 I can get seems to be around -12 dB. Sounds pretty miserable for resistive termination.

How is this done in practice?

PS: I am not interested in general answers to the reasons of matching and solutions outside IC context. Clearly off-chip matching networks may be a solution but I do not think this is what is used in the context of RFICs.

By purposefully making the bondwire longer (more L) and adding capacitance to Cpcb and Cpad, one could choose L, Cpcb and Ppad such that sqrt(L/C)=50 (e.g., L=3n, Cpcb=Cpad=1.2pF) I can bring S11 down to -20 dB or even more but this does not sounds like a practical option to me. Above all, -20 dB is not a good number in an "ideal" scenario either.

• To narrow things down a little, could you include an example of such an RFIC as you mention in your first paragraph. Perhaps depending on the type of signal, the mismatch is simply accepted (could be the case for a clock signal). I expect that playing with the bondwire length might be challenging as the length and shape of the bondwire might not be so predictable. Also in a CSP (flip-chip) package there are no bondwires. Apr 14 '17 at 9:01
• I really try hard to find now one of those. I remeber having seen this often but did not note down particularly. One reference that I find is Fig. 3.19, page 54 in doc.utwente.nl/82303/1/thesis_M_Soer.pdf. It can be seen that it is 100 Ohm here which is definitely suboptimal with bondwire. But actually I don't this this even matters: Even for an LNA (e.g. CGLNA) the issue should be the same: As soon as bondwire is added, the input impedance is not 1/20mS any more ...
– divB
Apr 14 '17 at 9:11
• what exactly is the problem you feel needs to be addressed? -20 is 'perfection' for chip matching, -12 is totally usable, depending on for what purpose. What part number were you using on what substrate into what line type for what purpose, and found the interface return loss what sort of a problem? Apr 14 '17 at 9:29
• Ha, University of Twente, my Alma mater ;-) Anyway, indeed in this example it is just a clock signal and they feed it into the chip differentially which helps with the matching. Also this is a research design, so no one cares if the matching is not OK, as long as the funtioning of the circuit can be demonstrated. Apr 14 '17 at 9:33
• ;-) The problem is how resistive matching with bondwire is done in practice. So if -20 is perfection and -12 (pre layout in sim) is useable, then maybe the answer to this question can be posted. (BG: I am working on a similar research project but for me I need to terminate the signal path with 50 Ohm. If there is nothing wrong by just placing a (possibly programmable) resistor right next to the pad and -12 is what would be acceptable (for my prototype is is probably because I can make the source side matching very good) then I'll go for that.
– divB
Apr 14 '17 at 10:25