It is widely known that resistive termination (e.g. 50 Ohm to ground) is superior when noise is no concern. Specifically in the block diagrams of RFICs I see many 50 Ohm resistors to ground directly driving a CMOS inverter buffer, when used as clock or LO pins.
This works obviously nice in the absence of parasitics but as soon as the bondwire and pad capacitances come into play, the concept of resistive termination fails for me. Consider the following example:
where the source resistance (50 Ohm) is fixed, Cpcb models the PCB pin, L the bondwire, Cpad the bonding pad on the die and Rt denotes a resistor to be chosen freely.
Not only is the optimum value NOT 50 Ohm but around 30 Ohm, also the best possible S11 I can get seems to be around -12 dB. Sounds pretty miserable for resistive termination.
How is this done in practice?
PS: I am not interested in general answers to the reasons of matching and solutions outside IC context. Clearly off-chip matching networks may be a solution but I do not think this is what is used in the context of RFICs.
By purposefully making the bondwire longer (more L) and adding capacitance to Cpcb and Cpad, one could choose L, Cpcb and Ppad such that sqrt(L/C)=50 (e.g., L=3n, Cpcb=Cpad=1.2pF) I can bring S11 down to -20 dB or even more but this does not sounds like a practical option to me. Above all, -20 dB is not a good number in an "ideal" scenario either.