I've been working on designing a discrete dual-slope ADC for school, and I've run into a problem. The schematic below shows my proposed input stage, an ideal integrator connected to a comparator. I've learned that you can reduce the input bias current by adding a compensating resistor to the non-inverting terminal of an op-amp.


simulate this circuit – Schematic created using CircuitLab

Since the capacitor behaves like an open circuit at DC, RC1 would presumably be the same value as R2, but I'm not sure how to compensate for the input bias current of the comparator. Here is what I've come up with so far:

Since the goal of a compensation resistor is to match the resistance seen by the two input terminals, I would expect RC2 to be the parallel combination of the output resistance of the op-amp and the input resistance of the comparator. In other words: \$R_{C2} = R_o \parallel R_{i+}\$. My problem is that both of those resistances are difficult to predict.


  • Is there some other way to compensate for the input bias current for the comparator? Is it necessary?
  • Will the input offset voltage and input bias current of the comparator have a significant effect on the op-amp integrator?
  • What other ways can I compensate?

I intend to use a precision op-amp and comparator.


1 Answer 1


The input resistance to the comparator is the output resistance of the integrator, and is less than an ohm. So the bias compensation would be the same - if you used one at all. However, consider that the voltage across such a resistor would be extremely small, and is swamped by the voltage offset of the comparator. So the compensation resistor can be dispensed with entirely. So

1) The resistor is unnecessary.

2) No. The op amp will put out whatever current is needed to produce the proper voltage at the input. It's one of the joys of negative feedback.

3) None needed.

  • \$\begingroup\$ When you say "the resistor," are you referring to RC1 or RC2 as being unecessary? Both? \$\endgroup\$ Commented Apr 15, 2017 at 1:05
  • \$\begingroup\$ RC 2. And, depending on your requirements, RC1 perhaps. Given your specific value of C, and the charging current through R1, it's quite possible that bias currents will be negligable - but that is for you to decide based on the details of your application. \$\endgroup\$ Commented Apr 15, 2017 at 2:36
  • \$\begingroup\$ Makes sense. It probably will depend on the sampling frequency I choose. \$\endgroup\$ Commented Apr 15, 2017 at 4:49
  • \$\begingroup\$ No, it's the time between resets of the integrator. ANY fixed current error into the integrator will produce a ramp which will lead in time to the integrator saturating. So any pure integrator which is not contained within a feedback loop requires a reset mechanism. The greater the ratio of input bias (not offset) current to capacitance, the shorter the reset interval. \$\endgroup\$ Commented Apr 15, 2017 at 15:51
  • \$\begingroup\$ That's what I meant. The integrator would be reset after each sampling period. \$\endgroup\$ Commented Apr 15, 2017 at 16:51

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