0
\$\begingroup\$

Going through the datasheet and the LPC17xx user manual, what is quite evident is how to select the various clocking options for the peripheral clock divider, i.e:

00   PCLK_peripheral = CCLK/4
01   PCLK_peripheral = CCLK
10   PCLK_peripheral = CCLK/2
11   PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.

But what is not evident is how various clock speeds impact the conversion time (or settling time) of the DAC output? Would CCLK / 8 result in longer settling times as compared to CCLK / 2?

In case if their exists no such relation and the conversion/settling time is only dependent upon the DAC BIAS bit (DACR[16]), then why did the designers even gave this option for choosing between different clock sources?

Please forgive me if i am asking something which is plainly obvious. ARM is a new architecture for me and i have searched through the available literature. I also checked out some tutorials but the question still remained unanswered.

CPU: LPC1768

|improve this question
\$\endgroup\$
  • \$\begingroup\$ The Vout of a DAC on an MCU is never quiet, because the MCU clocking/memory-read-write/outputdriver activity is always causing rail bounce and substrate bounce and injection of minority carriers that explore any and all paths back home. Can you define "settling"? Is there some TimeConstant you can trust? Does the MCU deterministic trash count? What SNR do you need? \$\endgroup\$ – analogsystemsrf Apr 15 '17 at 14:10
  • \$\begingroup\$ i understand your point but i am afraid this is not the question that i am asking, i am asking that what is the purpose of providing the DAC module a peripheral clock (along with programmable prescalars) when in practice it is using a Resistor String Architecture to simply latch the data within the specified settling time (which i think do not require programmable clock source). \$\endgroup\$ – Bhavneet Singh Bajwa Apr 17 '17 at 6:20
0
\$\begingroup\$

i think i now understand the reason as to why the designers provided a programmable peripheral clock to the DAC module.

It is usable for cases wherein we wish to use the DMA module to provide data to the DAC module. The peripheral clock is fed to a counter (writable via DACCNTVAL register) which generates a hardware interrupt (INT_DMA_REQ) which can be used by the DMA module to source data.

So, providing a peripheral clock with programmable prescalar along with a programmable counter helps to achieve all sorts of update rate.

|improve this answer
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.