Going through the datasheet and the LPC17xx user manual, what is quite evident is how to select the various clocking options for the peripheral clock divider, i.e:
00 PCLK_peripheral = CCLK/4 01 PCLK_peripheral = CCLK 10 PCLK_peripheral = CCLK/2 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.
But what is not evident is how various clock speeds impact the conversion time (or settling time) of the DAC output? Would CCLK / 8 result in longer settling times as compared to CCLK / 2?
In case if their exists no such relation and the conversion/settling time is only dependent upon the DAC BIAS bit (DACR), then why did the designers even gave this option for choosing between different clock sources?
Please forgive me if i am asking something which is plainly obvious. ARM is a new architecture for me and i have searched through the available literature. I also checked out some tutorials but the question still remained unanswered.