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Just from a theoretical perspective I would like to know what is the source impedance seen by an ADC peripheral. The analog signal (1kHz) is produced by an Instrumentation Amplifier, goes through a low pass and then reaches the ADC.

I think that this impedance would be the output impedance of the InAmp plus the resistor of the LP filter.
The problem is that i can't find the output impedance of the InAmp (AD8226) in the datasheet, i tried others InAmps from analog devices but none had this information.

edit1: Just to make it clear, i know that the ADC has it own impedance, but the source impedance also affects the minimum acquisition time, that's why i'm trying to figure out this source impedance. Does anyone has any tip ?adc_circuit

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    \$\begingroup\$ Open loop Rout is opamps is usually near 100 ohms. The circuits work out that way, for moderate output current ability. Wrap that 100 ohms inside a gain-of-1Million feedback loop, and you drop the 100 ohms to 100 microOhms. At DC. At higher frequencies, Rout becomes Zout, with phaseshifts; the Zout rises, looks inductive, and will oscillate with certain capacitive loads. More later. \$\endgroup\$ Commented Apr 16, 2017 at 17:26
  • \$\begingroup\$ I understand but why don't they state the impedance frequency dependence at a graph in the datasheet, like they usually do for other amplifiers. \$\endgroup\$ Commented Apr 16, 2017 at 18:01
  • \$\begingroup\$ More importantly, your ADC has an input impedance+capacitance that's listed in the uC's datasheet ;) \$\endgroup\$ Commented Apr 16, 2017 at 18:33
  • \$\begingroup\$ @analogsystemsrf datasheet shown load regulation error with 10k load being 1% so open loop Zo is not 100 -300 ohms like,BJT kinds. \$\endgroup\$ Commented Apr 16, 2017 at 19:28
  • \$\begingroup\$ Just to clarify terminology a bit: "input impedance" is the load that the ADC puts on the circuit driving it. Conversely, "source impedance" is the effective output impedance of the circuit driving the ADC. In other words, input impedance is what you see looking into the ADC input, while source impedance is what you see looking to the left from that point. Your question is about the effective source (output) impedance of the inamp and filter combination. \$\endgroup\$
    – Dave Tweed
    Commented Apr 16, 2017 at 20:52

5 Answers 5

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For clarity, I'm placing these 2 excerpts from the ADI datasheet into a separate "answer".

ADI shows 3 different interfaces from INA to ADC. The first interface is "low frequency". The accompanying text suggests accuracy requires R*C be slower than 5 microSeconds. At 5uS Filter Tau and 40kiloSamples/second (25uS period), you have 5Tau, if the acquisition time uses all the 40Ksam/sec time; each Tau provides 8.6dB of settling (or ~ 1.5 bits of ADC accuracy); thus you'll get no better than 43dB or 7.5 bits ADC. Why? The ADC has to re-acquire the sample, on its internal sample-hold capacitors, upon every new sample. Why? The stored charge gets consumed during the binary-search conversion. This need to re-charge will come across as failure-to-settle to 12 bits, or 16 bits, unless you allow time for 12 bit (40US) or 16bit (53uS).

What if the ADC only allows 50% of the period for sampling, because the other 50% is needed to perform the Binary Search conversion? enter image description here

Notice the ADI "Option 1" uses 100 ohms and 100nF, a 10uS Tau.

Here is the ADI "text"

enter image description here

The ADI text says "must stay above 5uS". Since the R*C example is 10uS, I think ADI means "must be slower than 5uS".

Below is screen shot from Signal Wave Explorer, using the included example of "Trapezoidal LowPass" (you can edit the waveform and the filter type). The RC period is 100 nanoseconds. For accurate (FFT) simulation, I used 1,000 samples for the input waveform.

On the output, note the red lines at 99.5nanoseconds (1 tau) and at 200nS. The 1 tau is 63% of final; the 2 tau is 86.5 % of final --- still 14.5% error. We thus have a statement of "accuracy"; the more settling we allow, the more accurate. 10 Tau is 10 nepers, or 10 * 8.6dB = 86 dB, or 14 bits.

enter image description here

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  • \$\begingroup\$ Hey, thank you very much, its a huge help. Let me ask you first how do you "each Tau provides 8.9dB of settling" ? And second in the solution 3, the tau is much faster 100 nS, because AD8616 can be stable at higher tau ? \$\endgroup\$ Commented Apr 17, 2017 at 16:32
  • \$\begingroup\$ The neper is 8.6 dB of accuracy in settling, provided by allowing 1 TAU of settling. If 2 Tau, 2 * 8.6 db. If 3 tau, 3 * 8.6dB. en.wikipedia.org/wiki/Neper \$\endgroup\$ Commented Apr 17, 2017 at 16:38
  • \$\begingroup\$ Alright, thank you so much for the enlightenment, so if i want to achieve the 12 bits of my adc i should, reduce the sampling rate to aprox. half , correct ? \$\endgroup\$ Commented Apr 17, 2017 at 18:43
  • \$\begingroup\$ analogsystemsrf, i would like to make you one more question. I was trying to get some more enlightenment about this subject and i came across this post electronics.stackexchange.com/a/269693/58365 regarding the cutting off frequency of the RC filter. And it says that with a sampling frequency , my frequency would be limited at 10 kHz and i would watch to achieve a -20db at this frequency so i would want to project the filter for a cut off frequency of 1KHz. Do you agree with this ? If you do, i would be degrading my signal, because i would be attenuating the 1KHz too. Ain't right ? :( \$\endgroup\$ Commented Apr 17, 2017 at 23:05
  • \$\begingroup\$ If you want 12 bits, and you are switching from one sensor to another sensor (with analog mux), that capacitor would need 8Tau to settle; however you are NOT switching sensors, thus that cap merely needs to track the INA output to within 1/2^12 or 1/4096; also that cap is HUGE compared to the ADC's internal sample-hold cap. \$\endgroup\$ Commented Apr 18, 2017 at 3:47
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Here is Zout for Enabled and Disabled of a highspeed OpAmp; the dip in Zout(disabled) at 500MHz is likely the resonance of Package / bondwire / silicon / testPCB inductance and the output capacitance of: ESD structures, and depletion / isolation regions of output drivers. To resonate at 500MHz, with 10nH (5nH of output pin, 5nH of VDD or 5nH of GND pins), requires 10pF. And that's about right.

How to interpret these two plots? The descending "Disabled" plot drops 20dB/decade, thus is capacitive. The ascending "Enables" plot rises 20db/decade, thus is inductive. We are not shown the phase shifts, but deduce that from the 20dB changes.

Notice the low drive level; -30dBm (50 ohms?) is 1/31.6 of 0.632vpp, thus 20mvpp. That drive level is low enough to not upset the operating conditions of the output transistors, even out past UGBW. UGBW is ~~ 200MHz for the ADA4896.

enter image description here

And now for a very low power (1uA Idd) opamp; notice the high frequency ( a relative term, for this slow opamp) Rout levels off at 80,000 ohms. Notice how the Zout for Av = 101 levels off near 80Kohm even for Frequency of 500Hz.

enter image description here

Notice how the G*H controls the Zout --- for high gain, there is little surplus loop gain to retain control of the output impedance. UGBW for this opamp? 10KHz.

Why is Zout important? As others mentioned, ringing occurs because of inductive Zout. And ringing affects Settling Time. I'm presently writing "rules" to synthesize precision-settling circuits, so need to document and manage all the gotchas.

Finally, Signal Chain Explorer has "OutZ", that looks backward into all prior stages interacting; here the Cshunt of 10uF interacts with OpAmp Zout (Rout is 100 Ohm). For clarity, I selected (clicked on) the "GainFollower" to display the "Amp Output Resistance-Open Loop" in the screen-shot. Previously I selected the "Capacitive Shunt" stage, then clicked "OutZ" to generate that lower right plot (Z, R, X) of "output impedance". Here is tutorial on measuring "output impedance". http://www.robustcircuitdesign.com/signal-chain-explorer/visualizing-op-amp-impedances-using-sce/ enter image description here

Here is the ADI INA topology; the output circuit is a standard commonmode stripper, thus expect the standard Inductive Zout behavior. enter image description here

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  • \$\begingroup\$ thanks for you affirmation that means something to me and +1 for yours and those who vote -1 (U know who you are) mean nothing to me without comments= except recipient has insufficient BW. \$\endgroup\$ Commented Apr 16, 2017 at 23:21
  • \$\begingroup\$ Hello, thank you for your answer. I'm am familiar with the Zout dependence on frequency and gain and this graph you showed is present in most of the amplifiers of OpAmp. But do you this i can make such a correlation to an InAmp ? \$\endgroup\$ Commented Apr 17, 2017 at 10:53
  • \$\begingroup\$ @user3689576 Yes, we can make such a correlation. The ADI Figure 58, on right side, shows the standard high-precision circuit to perform commonmode stripping. That circuit also has the Inductive Zout, in frequency region where the open loop gain is rolling off. \$\endgroup\$ Commented Apr 17, 2017 at 14:36
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For all practical purposes, at DC and very low frequencies, the closed loop output impedance of an amplifier with feedback can be regarded as zero ohms, as long as gain after feedback is reasonably low (that is, there's lots of loop gain to control the open loop output impedance).

At higher frequencies, the output impedance will rise. Some amplifiers specify this, often with a graph against frequency. If yours doesn't, you could try getting the manufacturer's SPICE model and simulating it, into your design load at your design frequency. If you're lucky, they'll have modelled in the open loop output impedance, as well as any output current limits which will limit the slew rate into a capacitive load.

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  • \$\begingroup\$ actually it is 100 Ohms with 0.1V load error with 10V swing with 10k load at unity gain, so not like traditional low Z OA's this is a R-R out CMOs high Zout 12mA current limited INA. No where near 0 ohms. \$\endgroup\$ Commented Apr 16, 2017 at 19:58
  • \$\begingroup\$ @TonyStewart.EEsince'75 I'd be interested to see a measurement of output impedance in the linear region. While I accept that current limiting will dent the output near the rails, I find it difficult to believe it's as high as 100ohms in the linear region, something as high as 100ohms would surely be specified, that the DC output impedance would be other than sqrt(buggerall). The output diff amp is configured with a noise gain of 2, ie humungeous closed loop gain. \$\endgroup\$
    – Neil_UK
    Commented Apr 17, 2017 at 5:40
  • \$\begingroup\$ Again I'm not looking for a practical approach. I want to know the impedance of InAmp because this affects my minimum ADC's acquisition time. But thanks. \$\endgroup\$ Commented Apr 17, 2017 at 10:54
  • \$\begingroup\$ @user3689576 you could always measure it. With a fixed input voltage, measure the output voltage unloaded, then with a resistor to ground (respecting its maximum output current), and do the sums. The only problem is, that's a practical approach, and you say you're looking for an impractical one??? \$\endgroup\$
    – Neil_UK
    Commented Apr 17, 2017 at 11:14
  • \$\begingroup\$ @Neil_UK , i'm currently projecting an circuit not actually testing it, so to make it go through i have to have my calculation done to make sure this IC fits my needs, namely if it meets my desired ADC sampling frequency. I know how to measure an impedance , but i always did this as a confirmation to backup a theoretical approach. I don't understand what is the motive for Analog Devices doesn't state in their InAmps the Impedance and its frequency and gain dependence. \$\endgroup\$ Commented Apr 17, 2017 at 11:38
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From this plot of ringing of the INA versus various capacitive loads, can we figure the Fring and thus the equivalent Zout Inductance? enter image description here

From peak-peak on pos and on neg edges, time is ~~ 0.3 * 1 division, or 1.2Usec. Thus 0.8MHz is the Fring. Given 0.8MHz is 5Mradian/second, the L*C product must be 1/(5Meg rad)^2 or 0.25*10^-14. At 100pF (10^-10), the Zout "inductor" must be 0.25 * 10^-4 Henry, or 25uH.

Do we have enough information, about G/(1 + GH), in this plot to determine the DC Rout?

enter image description here

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How not to design ADC with 1kHZ sine and 40ksps !

  • R = 100 , C = 0.5uF
  • H(f) @1kHz = -0.42dB (error)
  • H(2.4kHz) = -3dB
  • H(20kHz)= -16dB

Rather you need to define all the specs:

  • Input: amplitude range, frequency range, SNR input, Noise max V vs f
  • therefore noise reject = -x dB at f and <-60dB from signal at >=20kHz (1/2fs) pref well below below smallest signal and
  • gain error in passband = __
  • offset error ___
  • loading error 175ppm >2kohm at Av=1000 given.
  • Limits to rail to rail given, for different loads, given (V-0.2V) at 2k, (V-0.1V at 10k)

  • Define Error budget: Gain, Offset, Nyquist filter alias error. INA loading error, ADC linearity error, Monotonicity error , Temp drift error, Vibration error (ceramics), Supply sensitivity error

Summary comments

We call this an XY question, You state the problem as X but the real problems are Y.

For a better answer to X read specs for PPM error vs gain >2k load and error vs Zload at rail.

For the Y problems

What are the Nyquist filter requirements? What is the exact signal input and ADC range, what noise from EMI in cable and sensor will affect from poor CMRR from impulse noise?

What is your total accuracy spec or error budget??


All active devices have a DC output impedance and BJT's OA's suffer from voltage drop from Vcc Vee while Rail-rail output OA's/INA's use MOSFETs tend to have lower currents due to higher voltage design and prevention of shotthru failures. So this INA must use lighter impedance loads or less cap charge currents to enable faster response time.

We also know negative feedback can reduce the impedance towards zero due to Zout(open loop)/Feedback gain. Thus if open loop gain is 1e6 and closed loop gain is 10 then feedback is 1e5 and Zout_dc =Zo1/1e5 for this example. We known GBW reduces open loop gain and thus feedback so Zout_ac rises due to reduced Aol with rising frequency.

Reading the datasheet we find Zout but load regulation calculation like a voltage divider.

RL =10kΩ to 1.35V with +/-13 V signals on +/-15 supplies, Vout_dc error = +/-0.1V

this is approximately 0.1/10V or 1% load regulation error using 10k load with unity gain or 1e5 to 1e6 est.open loop gain.

This implies Zout open loop (if possible ) would be very high, which is why max gain is 1k but then it is rail to rail with no shoot thru and draws very little current. so pay attention load caps and sample duration.

Thus adding 100 Ohm to closed loop gain rises the output Z and then adding a cap lowers the Zo_ac according to R+1/2pifC + its ESR value. It could be as high as 10k at 1MHz. Good response with 47pF is shown but not shown with ADC dynamic input impedance if it exists. (if buffered better)

Best choice is NPO or a plastic cap, which is very low. (caution only use NPO if using ceramic for lowest ESR and load regulation transients from ADC switched capacitor S&H as well as memory effects from non NPO ceramic dielectric absorption. Thus sampling error and setting time are a careful selection of C values such as 47pf and depends on input C of ADC when sampled for a C divider ratio and setting time.

Noise and sampling rates are tradeoffs with Zout_ac and Zin_ac of the ADC at high speed sampling rates.

Even For low speed ADC it's " noise" and must be considered unless the sample time is controlled.

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  • \$\begingroup\$ @ Tony Lotta good details here. Shame to build a high performance system, and have the pre-ADC filter cap dielectric absorption cause ISI. \$\endgroup\$ Commented Apr 16, 2017 at 22:50
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    \$\begingroup\$ I think i calculated Zout with wrong INA data . Sheet. I shud've included non-linearity for rising ppm error numbers for 2k load with gains of 1, 100, 1000 but no one else figured that out yet. and extreme V error of 0.4V, 0.2V and 0.1V for 2k, 10k, 100k \$\endgroup\$ Commented Apr 16, 2017 at 23:20
  • \$\begingroup\$ Hei @TonyStewart.EEsince'75,thanks for your answer. But there is a lot of things i don't understand but i really want to. First of all, let me be more clear about my case. The signal that reaches the ADC is sinusoidal wave with 1KHz, i'm sampling at 40 kHz. I want to know what is output impedance, because reading my uC(PIC18F26J13) ADC's datasheet, its stated that the ADC charging capacitors is dependent on the impedance of the ADC block plus the source impedance, thus the minimum acquisition time to meet the ADC specs is too. So thats my obsession about the output impedance. \$\endgroup\$ Commented Apr 17, 2017 at 11:49
  • \$\begingroup\$ Regarding your answering and forget the impedance of the filter, is it possible to know theoretically the approximate impedance of the InAmp amplifier for a 1kHz signal and a unity gain , in order to can calculate what is the minimum acquisition time i need ? (besides the low pass filter RC restrain, offcourse) \$\endgroup\$ Commented Apr 17, 2017 at 11:53
  • \$\begingroup\$ read my update XY problem. define specs 1st !!!! \$\endgroup\$ Commented Apr 17, 2017 at 13:49

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