Output Impedance of Instrumentation Amplifier

Question

Just from a theoretical perspective I would like to know what is the source impedance seen by an ADC peripheral. The analog signal (1kHz) is produced by an Instrumentation Amplifier, goes through a low pass and then reaches the ADC.

I think that this impedance would be the output impedance of the InAmp plus the resistor of the LP filter.
The problem is that i can't find the output impedance of the InAmp (AD8226) in the datasheet, i tried others InAmps from analog devices but none had this information.

edit1: Just to make it clear, i know that the ADC has it own impedance, but the source impedance also affects the minimum acquisition time, that's why i'm trying to figure out this source impedance. Does anyone has any tip ?

Answer 1

For clarity, I'm placing these 2 excerpts from the ADI datasheet into a separate "answer".

ADI shows 3 different interfaces from INA to ADC. The first interface is "low frequency". The accompanying text suggests accuracy requires R*C be slower than 5 microSeconds. At 5uS Filter Tau and 40kiloSamples/second (25uS period), you have 5Tau, if the acquisition time uses all the 40Ksam/sec time; each Tau provides 8.6dB of settling (or ~ 1.5 bits of ADC accuracy); thus you'll get no better than 43dB or 7.5 bits ADC. Why? The ADC has to re-acquire the sample, on its internal sample-hold capacitors, upon every new sample. Why? The stored charge gets consumed during the binary-search conversion. This need to re-charge will come across as failure-to-settle to 12 bits, or 16 bits, unless you allow time for 12 bit (40US) or 16bit (53uS).

What if the ADC only allows 50% of the period for sampling, because the other 50% is needed to perform the Binary Search conversion?

Notice the ADI "Option 1" uses 100 ohms and 100nF, a 10uS Tau.

Here is the ADI "text"

The ADI text says "must stay above 5uS". Since the R*C example is 10uS, I think ADI means "must be slower than 5uS".

Below is screen shot from Signal Wave Explorer, using the included example of "Trapezoidal LowPass" (you can edit the waveform and the filter type). The RC period is 100 nanoseconds. For accurate (FFT) simulation, I used 1,000 samples for the input waveform.

On the output, note the red lines at 99.5nanoseconds (1 tau) and at 200nS. The 1 tau is 63% of final; the 2 tau is 86.5 % of final --- still 14.5% error. We thus have a statement of "accuracy"; the more settling we allow, the more accurate. 10 Tau is 10 nepers, or 10 * 8.6dB = 86 dB, or 14 bits.

Answer 2

Here is Zout for Enabled and Disabled of a highspeed OpAmp; the dip in Zout(disabled) at 500MHz is likely the resonance of Package / bondwire / silicon / testPCB inductance and the output capacitance of: ESD structures, and depletion / isolation regions of output drivers. To resonate at 500MHz, with 10nH (5nH of output pin, 5nH of VDD or 5nH of GND pins), requires 10pF. And that's about right.

How to interpret these two plots? The descending "Disabled" plot drops 20dB/decade, thus is capacitive. The ascending "Enables" plot rises 20db/decade, thus is inductive. We are not shown the phase shifts, but deduce that from the 20dB changes.

Notice the low drive level; -30dBm (50 ohms?) is 1/31.6 of 0.632vpp, thus 20mvpp. That drive level is low enough to not upset the operating conditions of the output transistors, even out past UGBW. UGBW is ~~ 200MHz for the ADA4896.

And now for a very low power (1uA Idd) opamp; notice the high frequency ( a relative term, for this slow opamp) Rout levels off at 80,000 ohms. Notice how the Zout for Av = 101 levels off near 80Kohm even for Frequency of 500Hz.

Notice how the G*H controls the Zout --- for high gain, there is little surplus loop gain to retain control of the output impedance. UGBW for this opamp? 10KHz.

Why is Zout important? As others mentioned, ringing occurs because of inductive Zout. And ringing affects Settling Time. I'm presently writing "rules" to synthesize precision-settling circuits, so need to document and manage all the gotchas.

Finally, Signal Chain Explorer has "OutZ", that looks backward into all prior stages interacting; here the Cshunt of 10uF interacts with OpAmp Zout (Rout is 100 Ohm). For clarity, I selected (clicked on) the "GainFollower" to display the "Amp Output Resistance-Open Loop" in the screen-shot. Previously I selected the "Capacitive Shunt" stage, then clicked "OutZ" to generate that lower right plot (Z, R, X) of "output impedance". Here is tutorial on measuring "output impedance". http://www.robustcircuitdesign.com/signal-chain-explorer/visualizing-op-amp-impedances-using-sce/

Here is the ADI INA topology; the output circuit is a standard commonmode stripper, thus expect the standard Inductive Zout behavior.

Answer 3

For all practical purposes, at DC and very low frequencies, the closed loop output impedance of an amplifier with feedback can be regarded as zero ohms, as long as gain after feedback is reasonably low (that is, there's lots of loop gain to control the open loop output impedance).

At higher frequencies, the output impedance will rise. Some amplifiers specify this, often with a graph against frequency. If yours doesn't, you could try getting the manufacturer's SPICE model and simulating it, into your design load at your design frequency. If you're lucky, they'll have modelled in the open loop output impedance, as well as any output current limits which will limit the slew rate into a capacitive load.

Answer 4

From this plot of ringing of the INA versus various capacitive loads, can we figure the Fring and thus the equivalent Zout Inductance?

From peak-peak on pos and on neg edges, time is ~~ 0.3 * 1 division, or 1.2Usec. Thus 0.8MHz is the Fring. Given 0.8MHz is 5Mradian/second, the L*C product must be 1/(5Meg rad)^2 or 0.25*10^-14. At 100pF (10^-10), the Zout "inductor" must be 0.25 * 10^-4 Henry, or 25uH.

Do we have enough information, about G/(1 + GH), in this plot to determine the DC Rout?

Answer 5

How not to design ADC with 1kHZ sine and 40ksps !

• R = 100 , C = 0.5uF
• H(f) @1kHz = -0.42dB (error)
• H(2.4kHz) = -3dB
• H(20kHz)= -16dB

Rather you need to define all the specs:

• Input: amplitude range, frequency range, SNR input, Noise max V vs f
• therefore noise reject = -x dB at f and <-60dB from signal at >=20kHz (1/2fs) pref well below below smallest signal and
• gain error in passband = __
• offset error ___
• loading error 175ppm >2kohm at Av=1000 given.

• Limits to rail to rail given, for different loads, given (V-0.2V) at 2k, (V-0.1V at 10k)

• Define Error budget: Gain, Offset, Nyquist filter alias error. INA loading error, ADC linearity error, Monotonicity error , Temp drift error, Vibration error (ceramics), Supply sensitivity error

Summary comments

We call this an XY question, You state the problem as X but the real problems are Y.

For a better answer to X read specs for PPM error vs gain >2k load and error vs Zload at rail.

For the Y problems

What are the Nyquist filter requirements? What is the exact signal input and ADC range, what noise from EMI in cable and sensor will affect from poor CMRR from impulse noise?

What is your total accuracy spec or error budget??

---

All active devices have a DC output impedance and BJT's OA's suffer from voltage drop from Vcc Vee while Rail-rail output OA's/INA's use MOSFETs tend to have lower currents due to higher voltage design and prevention of shotthru failures. So this INA must use lighter impedance loads or less cap charge currents to enable faster response time.

We also know negative feedback can reduce the impedance towards zero due to Zout(open loop)/Feedback gain. Thus if open loop gain is 1e6 and closed loop gain is 10 then feedback is 1e5 and Zout_dc =Zo1/1e5 for this example. We known GBW reduces open loop gain and thus feedback so Zout_ac rises due to reduced Aol with rising frequency.

Reading the datasheet we find Zout but load regulation calculation like a voltage divider.

RL =10kΩ to 1.35V with +/-13 V signals on +/-15 supplies, Vout_dc error = +/-0.1V

this is approximately 0.1/10V or 1% load regulation error using 10k load with unity gain or 1e5 to 1e6 est.open loop gain.

This implies Zout open loop (if possible ) would be very high, which is why max gain is 1k but then it is rail to rail with no shoot thru and draws very little current. so pay attention load caps and sample duration.

Thus adding 100 Ohm to closed loop gain rises the output Z and then adding a cap lowers the Zo_ac according to R+1/2pifC + its ESR value. It could be as high as 10k at 1MHz. Good response with 47pF is shown but not shown with ADC dynamic input impedance if it exists. (if buffered better)

Best choice is NPO or a plastic cap, which is very low. (caution only use NPO if using ceramic for lowest ESR and load regulation transients from ADC switched capacitor S&H as well as memory effects from non NPO ceramic dielectric absorption. Thus sampling error and setting time are a careful selection of C values such as 47pf and depends on input C of ADC when sampled for a C divider ratio and setting time.

Noise and sampling rates are tradeoffs with Zout_ac and Zin_ac of the ADC at high speed sampling rates.

Even For low speed ADC it's " noise" and must be considered unless the sample time is controlled.