How not to design ADC with 1kHZ sine and 40ksps !
- R = 100 , C = 0.5uF
- H(f) @1kHz = -0.42dB (error)
- H(2.4kHz) = -3dB
- H(20kHz)= -16dB
Rather you need to define all the specs:
- Input: amplitude range, frequency range, SNR input, Noise max V vs f
- therefore noise reject = -x dB at f and <-60dB from signal at >=20kHz (1/2fs) pref well below below smallest signal and
- gain error in passband = __
- offset error ___
- loading error 175ppm >2kohm at Av=1000 given.
Limits to rail to rail given, for different loads, given (V-0.2V) at 2k, (V-0.1V at 10k)
Define Error budget: Gain, Offset, Nyquist filter alias error. INA loading error, ADC linearity error, Monotonicity error , Temp drift error, Vibration error (ceramics), Supply sensitivity error
We call this an XY question, You state the problem as X but the real problems are Y.
For a better answer to X read specs for PPM error vs gain >2k load and error vs Zload at rail.
For the Y problems
What are the Nyquist filter requirements? What is the exact signal input and ADC range, what noise from EMI in cable and sensor will affect from poor CMRR from impulse noise?
What is your total accuracy spec or error budget??
All active devices have a DC output impedance and BJT's OA's suffer from voltage drop from Vcc Vee while Rail-rail output OA's/INA's use MOSFETs tend to have lower currents due to higher voltage design and prevention of shotthru failures. So this INA must use lighter impedance loads or less cap charge currents to enable faster response time.
We also know negative feedback can reduce the impedance towards zero due to Zout(open loop)/Feedback gain. Thus if open loop gain is 1e6 and closed loop gain is 10 then feedback is 1e5 and Zout_dc =Zo1/1e5 for this example. We known GBW reduces open loop gain and thus feedback so Zout_ac rises due to reduced Aol with rising frequency.
Reading the datasheet we find Zout but load regulation calculation like a voltage divider.
RL =10kΩ to 1.35V with +/-13 V signals on +/-15 supplies, Vout_dc error = +/-0.1V
this is approximately 0.1/10V or 1% load regulation error using 10k load with unity gain or 1e5 to 1e6 est.open loop gain.
This implies Zout open loop (if possible ) would be very high, which is why max gain is 1k but then it is rail to rail with no shoot thru and draws very little current. so pay attention load caps and sample duration.
Thus adding 100 Ohm to closed loop gain rises the output Z and then adding a cap lowers the Zo_ac according to R+1/2pifC + its ESR value. It could be as high as 10k at 1MHz. Good response with 47pF is shown but not shown with ADC dynamic input impedance if it exists. (if buffered better)
Best choice is NPO or a plastic cap, which is very low. (caution only use NPO if using ceramic for lowest ESR and load regulation transients from ADC switched capacitor S&H as well as memory effects from non NPO ceramic dielectric absorption. Thus sampling error and setting time are a careful selection of C values such as 47pf and depends on input C of ADC when sampled for a C divider ratio and setting time.
Noise and sampling rates are tradeoffs with Zout_ac and Zin_ac of the ADC at high speed sampling rates.
Even For low speed ADC it's " noise" and must be considered unless the sample time is controlled.