# Voltage Multiplier - Cockcroft-Walton Capacitance Value

I want to design a circuit in order to Harvest radio-frequency (RF) signals and get a DC Output to a specific load (i.e micro Watt Battery of a sensor).

Notes to be considered :

• input will be between (uV - mV) which is low.
• frequency that i am harvesting from is the GSM frequency which is 900-915 MHz
• considering this frequency value the capacitance should be really small (pico or nano farads)

During my research i have found that the most used step-up (In terms of Voltage) configurations are mainly three types which are :

1- Transformer Topology (Which is the cheapest and less efficient for such application)

2-Diodes : Rectifiers (Which I am not interested in due to losses)

3-Voltage Doubler/ Multiplier (Which consists of diodes and capacitors such like >> Cockcroft-Walton or any other configuration)

Now the thing is that there are a lot of types of the voltage multiplier, but I could not find any certain reference that can help me through the design of the Voltage multiplier.

For example how to calculate the capacitance values lets say for multi-stage multiplier with N Stages and Vin to Vout specific ratio ?

Such as : Vin = 1V Vout = 5V N = 5-10 stages (or more depending on the output)

Cockcroft-Walton Topology with 2 stages.

Any advice will be much appreciated

• There are lots of good web pages on the design aspect here. You will find that the capacitor's value depends heavily on the required output current. (Look up Dickson as well as Cockcroft-Walton, in your case, I suspect.) However, I don't think this is a way to harvest RF energy. Texas Instruments is very busy in this area. You should visit their site. – jonk Apr 16 '17 at 20:19
• Voltage multipliers use diodes just as a bridge rectifier does. You will have problems with the forward voltage whether you use a bridge rectifier or a voltage multiplier. – JRE Apr 16 '17 at 20:27
• But the idea is that cascaded capacitors with diodes are going to multiply the value of the voltage in a certain manner .. – MN93 Apr 16 '17 at 20:30
• @jonk this is only part of the harvesting circuit.. – MN93 Apr 16 '17 at 20:32
• What makes you think this will work without at least -20dBm and an antenna impedance matching network? Not possible as shown in schematic – Tony Stewart Sunnyskyguy EE75 Apr 16 '17 at 20:36

Start at a minimum of 10uW/cm² or -20dBm/cm² or 5 mV/mm E-field.

# Needs impedance matched antenna complete circuit

Use a tuned rectangular patch antenna or rectenna with impedance matching network then smallest Cockcroft–Walton doublers into an open loop *with π/4 to π/2 radius..errhm I meant λ/4 to λ/2 radius... with suitable transmission line impedance matching striplines and at least 10 stages.

## Need variable f generator

to measure s21 or DC out with f input

Another method is use Bennet doubler using e-VEH with a motion of 5mm_DA at low frequency ( e.g. 10~30 Hz) to demodulate the steady amplitude RF field.

## Sch. Diodes must be low C and ESL

Low parasitic impedance: C< 0.05 pF, Ls < 0.2 nH

## Dielectric substrate must be low loss tangent

like ceramic, teflon or special polyamide or https://plastics.ulprospector.com/datasheet/e120881/arlon-25n

## must be small SMT for diode low pF for loop antenna

like 0201 SMD suitable for >>10GHz to prevent C divider loading and great efficiency.

## Choose largest RF cap possible in smallest package e.g 0201 if possible.

• use reputable suppliers with s parameters like Murata, TDK etc.
• must be very low loss tangent NPO type material or better ceramic
• Consider 50~100pF with much higher SRF.

Expect 1V at maybe >> -15dBm and 3.3V at -5dBm with > 10 stages

## other

• There is always an optimum limit to n- stage doublers based on impedance ratios and loads, leakage.

• plan on $200 budget for proto unless you get free samples for all materials. (ha!) • Thanks for the detailed answer .. so correct me if i am wrong the capacitors values are preferred to be in pico or nano.. and experimentally i can decide which value suits more right ? – MN93 Apr 16 '17 at 21:25 • only pF <100 or as long as SRF>>>1GHz with 10 stages. 20 yrs ago the optimal 603 cap was 47pF at 1GHz, go smaller size bigger value with reflow board. – Tony Stewart Sunnyskyguy EE75 Apr 16 '17 at 21:26 • that should save you at least$10k R&D man-hours – Tony Stewart Sunnyskyguy EE75 Apr 16 '17 at 21:29
• I forgot to mention if diode pF is too large, then you can only demodulate carrier AM rather RF cycle and then need 90% AM , not found in Cell radios or WiFi and signal must be larger then. – Tony Stewart Sunnyskyguy EE75 Apr 16 '17 at 22:15