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I am setting up a audio delay circuit and i want to store the data on SRAM chip.

I am doing it with a 64khz clock and ideally i would like to write a word in every other pulse and read a word every other pulse so i'm reading and writing at 32khz - with a distance between the word addresses of course.

http://www.alliancememory.com/pdf/AS6C2016.pdf this is the link to the datasheet...

I was wondering if anyone knows a clever way to alternate addresses with 2 different 16 bit binary counters? or maybe there is an easier way in general to fulfill this task?

Also there isn't a clock pin on this chip which is confusing... do i just oscillate the "chip enable" pin?

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Alternatively, you could use a FIFO like this one. These are available with enough memory. Also, you can easily have a variable delay. Simply delay the reading for N milliseconds after the write begins, and you have N milliseconds delay.

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  • \$\begingroup\$ hmm never heard of FIFO.. I'm going to check this out... looks like it has time saving potential. \$\endgroup\$ – Emery King Apr 16 '12 at 3:16
  • \$\begingroup\$ Does the memory wrap as i'm loading? or do i have to reset it when it's full? If it wraps then this is awesome! \$\endgroup\$ – Emery King Apr 16 '12 at 3:33
  • \$\begingroup\$ Never mind I've since figured this out. It's only full if the writing word tries to lap the reading word basically. \$\endgroup\$ – Emery King Apr 16 '12 at 5:05
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What would be ideal would be if you could have two counters which included three-state output drivers, so you could easily alternate between the values. Unfortunately, I don't know of any such beast. Your best bet if you want to use discrete logic is probably to use a counter each for read and write addresses, and then either a multiplexer or two sets of 3-state driver chips.

If all you're trying to do, however, is generate a programmable delay, you might be better off reading and writing the same address. Control your delay amount by either using a presettable counter which gets loaded each time it hits zero, a resettable counter with a circuit to detect when it reaches a programmable threshold, or a variable frequency clock.

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    \$\begingroup\$ i'm trying to initially delay the audio so its always 1/5th second behind. using a microphone input. so the storing 1 word in a counter/gate thing would only be useful for 1 word and i need to store thousands in that 1/5th of a second at 32khz sampling rate. \$\endgroup\$ – Emery King Apr 15 '12 at 20:16
  • \$\begingroup\$ yeah so how would i switch between the counters for each address? i would have to do a flip flop on each pin as far as i know... \$\endgroup\$ – Emery King Apr 15 '12 at 20:17
  • \$\begingroup\$ If you use a 40,960Khz sampling rate, then a 13-bit counter would loop every 1/5 second. If you use a single counter, one would alternate between reading an address (outputting to a DAC the audio from 1/5 second before), and then writing that same address with value from the ADC. Then advance to the next address and repeat. If you wanted to use two counters (e.g. so one could 'wobbulate' the sound by varying their speeds independently) one should tie the output from each counter to the inputs of a couple 74HC373's, and tie the outputs of both counters' 74HC373's... \$\endgroup\$ – supercat Apr 15 '12 at 20:25
  • \$\begingroup\$ ...together. So counter 1 bit 0-7 would feed into D0-D7 of one 74HC373; counter 2 bit 0-7 would feed D0-D7 of a second 74HC373. Outputs Q0-Q7 of both of those 74HC373's would feed address pins 0-7. For address bits 8-12 (or 8-15, or whatever) use another pair of 74HC373's. Each 74HC373 has an output-enable line; enabling one 74HC373 would cause its counter bits to drive the address bus. If desired, the latch inputs of the 74HC373's could be strapped high, or one could use the latches to ease timing constraints elsewhere. \$\endgroup\$ – supercat Apr 15 '12 at 20:28

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