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Why does the peripheral clock(Fp) & cpu clock(Fcy) is half of the system clock in DSpic & 24F devices and quarter of it in DSpic30f & 8 bit PIC series. Does this have something to do with the number of stages in pipelining ?

Dspic33ep64gs804 Osc diagram

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  • \$\begingroup\$ Can you provide a link to the datasheet where the block diagram came from?? There seems to be a footnote for Fcy and Fp which probably explains or hints as why those clock are divided by 2 \$\endgroup\$ – Kvegaoro Apr 17 '17 at 14:41
  • \$\begingroup\$ ww1.microchip.com/downloads/en/DeviceDoc/70005258b.pdf \$\endgroup\$ – Dogus Ural Apr 17 '17 at 16:23
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It's because The CPU needs 2 (dsPIC33/PIC24F) or 4 (8 bit PIC) clocks per instruction cycle, but the peripherals only need 1 clock.

On 8 bit PICs each instruction cycle consists of 4 'Q' cycles:-

  • Q1: Instruction Decode Cycle or forced No Operation
  • Q2: Instruction Read Cycle or No Operation
  • Q3: Process the Data
  • Q4: Instruction Write Cycle or No Operation

Each 'Q' cycle requires 1 oscillator clock, so instruction cycle frequency (Fcy) = Fosc/4.

This is not related to pipelining, which is applied to the entire instruction cycle. 8 bit PICs have a simple 2 stage pipeline where the next instruction is fetched at the same time as the current instruction is being executed.

enter image description here

dsPIC33/PIC24F have a multistage pipeline which starts fetching the instruction half way through the CPU cycle, then takes up to 9 cycles to complete the fetch and execute. On these MCUs Fcy = Fosc/2.

enter image description here

Compared to other MCUs which have equal instruction and clock cycle timing, 16 bit PICs are 2 times slower and 8 bit PICs are 4 times slower. An 8 bit PIC running at 64MHz is equivalent to an 8 bit AVR running at 16MHz.

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The reason behind this is to do with the architecture of the PIC microcontrollers, and to do with the number of clock cycles per instruction.

On the PIC 8-bit series, each instruction takes 4 clock cycles to execute. As such the CPU needs to run 4 times faster than the peripherals in order to stay in sync. Imagine if you were trying to update a timer but it was counting 4 times faster than you could execute instructions - you'd end up with a synchronisation issue.

The DSPic series as far as I recall also takes 4 clock cycles to execute each instruction.

For the 24F series, I am surmising (could check I supposed) that it takes 2 clock cycles per instruction - I've not checked though.

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Power is a big factor, you cant really get at the peripherals that fast, and they dont do things that fast normally so no reason to overclock them and waste power.

This is not limited to Microchip or PICs this is fairly common, esp with chips that have a wide range for the system/cpu clock. Some will force a divisor, some will make it programmable with a default and then provide a specification for each, this one cant exceed X Mhz, that one Y Mhz and the cpu/system cannot exceed Z Mhz.

You ideally want to make each clock as slow as you can tolerate and still perform the function in order to save power.

If/when you have a very limited range or only on clock speed supported there would be no surprise if they hardcoded the divisor for you.

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