How can inductance affect push pull converter?

Question

I'm trying to figure out the effect of adding inductance to a push pull topolgy but there are many parameters and I got confused.

First of all, considering the previous basic circuit, What limits the current when one of the mosfets is one? Isn't it the inductance and the resistance (though the reistance is very small ) of the primary winding ? so what bother if I added another inductance (I mean the inductive resistor at the bottom) to the path?

And would it change anything if I put this inductive resistor at the high side (regarding the switching speed of mosfets)?

Can't this inductance acts somehow as a lowpass filter and filters some of the high frequency components of the PWM singal (which is 10 Khz sine pwm)? and if yes, wouldn't that be a good thing for the 50 hz transformer?

I asked this question becuase of the answers of my other question about the very low value resistor and some mentioned that my resistor is inductive and can cause issues in switching circuits so I wanted to know its effect on my particualr application and it seemed to my little knowledgement of electronics that it has advantages not the opposite (electronics is really too tricky to me).

Answer 1

I assume you know these;

\$Z_L(f)=2\pi fL\$

For a split transformer with a full bridge drive at twice V and twice source impedance \$(R_{dsOn}+DCR/2)\$ where DCR is the full primary coil DC R.

transformer \$Z_{out}= 1:n^2*Z_{s}\$ for secondary out and driver source

Current Rise time= \$2L/R\$ should be <<10% of cycle because driver Pd must be close to square wave but I continues when V rises to full voltage thus SOA peak loss must be considered during T transition time.

This is how you calculate L and DCR must be <<5% of \$Z_L(f)\$ to minimize conduction losses according to your efficiency specs. The lower RdsOn MOSFETs also have greater Coss so the MOSFET must be carefully selected with L of transformer to achieve the lowest losses but highest Self Resonance Frequency. These are tradeoffs with DCR, core permeability, winding turn , Inductance Turns ratio switching frequency, rise time and generally the higher the f, the smaller the core is possible which is of course unsuitable for line rates.

This is just a snapshot or introduction to transformer design and not the whole process.

If Max power transfer @ Load= Zout but efficiency is only 50% so you choose the V out and Zload to maximize efficiency vs Pout by the impedance ratios from above. Short circuit currents are related to Zo output of the transformer normalized on a per unit p.u. basis so that 1/Zo% is a ratio of the rated current. One must be careful never to exceed the saturation current level to avoid massive conduction losses due to a huge drop in primary inductance when saturated. Good Ferrite is around 0.7T while good silicate coated Cold Rolled Silicon Steel (CRSS) for line frequency is around 1.6T to 2T for more expensive materials.

When choose switching fundamental frequency. L must be changed with f and turns ratio. Higher L for higher n step up and lower if step down.

• If step up turns ratio n, then primary inductance must be increase \$n^2\$
• if frequency is lowered 4 decades then primary inductance must be increased 4 decades.