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I'm trying to build some logic gates out of transistors to eventually be able to make a full adder circuit. I've tried building a NAND gate multiple times but I can't seem to be able to get it right. I've looked at lots of different pictures of them and all of them appear to have 3 resistors on them. I only ever put 2 in mine (R2 and R3 in this example) and I'm wondering whether my failures lie in not adding the third resistor (R1). I understand why R2 and R3 are there - to limit the current going from base to emmiter - however I don't understand why R1 is there.

So my question is why is R1 there and what is it's use in the circuit?

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ If R1 weren't there are you considering replacing it with a wire or an open circuit? \$\endgroup\$ – The Photon Apr 17 '17 at 17:02
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Since you are interested in attempting an adder with RTL (resistor-transistor logic), let me help you avoid some trouble and offer a designed gate for you:

schematic

simulate this circuit – Schematic created using CircuitLab

As you probably know, any OR gate can be converted to an equivalent AND gate. So I show both in the display.

The reason I'm including a designed element without going into the design details here (if you want, you can go here to find some of those details explained) is that it doesn't seem (from your question) that you are ready for it. But you are ready to start trying your hand at fabrication. And that's fine, I think. It's a good way to get into the idea more and develop motivation to do more.

Above, you only need one NPN BJT per gate and it's been designed to work reasonably well with small signal BJTs like the 2N3904 and the 2N2222 (aka PN2222.) I am offering you a NOR gate here because it uses an NPN and they may be a little cheaper, possibly more readily available, and have a little more current gain than equivalent PNPs. But if you have a lot of PNPs floating around, then I provide the equivalent PNP NAND gate later below.


A short explanation may suffice. \$Q_1\$ acts to invert its input. It does this because the transistor will pull it's collector very close to its emitter if enough (recombination) current is supplied to its base. Since the emitter is tied to ground and since ground is considered as the "0" symbol (a voltage sufficiently above ground is considered to be a "1" symbol), the output will be "0" when that base current is supplied. Otherwise, the collector won't be pulled towards its emitter (it will just "float") and then \$R_C\$ will be able to "pull upwards" towards the \$+5\:\textrm{V}\$ supply rail, making the output a "1" (sufficiently above ground.)

It turns out that either one of the two input resistors, shown as \$R\$ in the schematic, are sufficient. So if either of those are "pulled up" towards the \$+5\:\textrm{V}\$ supply rail, then \$Q_1\$ will pull its collector close to its emitter. Since pulling up is a "1", this means that if \$A\$ or else \$B\$ is pulled up, then the output will be "0". In short, the output is \$\overline{A + B} \leftrightarrow \overline{A}\cdot\overline{B}\$.

You can build an adder from these just as easily as you can from a NAND gate.


If you actually do want a NAND gate, you can make it using a PNP, instead:

schematic

simulate this circuit

It's really just the exact same design. PNP transistors will typically have a little less DC current gain (\$\beta\$) than similar NPN transistors, but the original NPN version was designed to accept a wide range on that parameter. So it should work fine without any changes to the resistor values.


Here's what you are facing, though, to make just a single "full adder" circuit with the NOR gate (you can replace each NOR with a NAND gate, equivalently):

enter image description here

So that gives you an idea about what your protoboard might look like in developing an adder for just one bit. If you want to add four bits, you'll need about four of those sections to get there (with ripple carry.)

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If R1 was not there your output would be tied to the rail...how could you ever pull it down?

You COULD leave R1 and the rail out and it would be an open collector NAND gate though, but at some point you would need a pull-up or some other load to the upper rail.

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R1 is a pull-up resistor. This forces the output to go high when neither input A or B are high. If you replaced R1 with a short, then your output would always be high and would never be pulled low, even if inputs A and B are high. R1 is critical to the operation of a NAND gate like this built around BJTs.

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If you do not have any base current Vc goes to 6.

If you don't have a resistor with correct value as shown, it can't sink up to 10x base current or limited by V+/Rc to saturate Vce.

6V must match input limits for logic load.

usually <1/3 Vdd to >2/3Vdd for CMOS if rated for 6V. some are not!

If Rc=0 , what Ic do you expect with 6V on both A and B ? 10x Ib ? no since Vce=6V 200xIb? possibly then what is Pd ? (6-1.2V)/10*200= 100mA approx x 5V = very transistor at 0.5W and likely shorted out at ~5-8x Pd rating

For historical purposes pls review TTL design practise. Then move on to CMOS.

http://www.ti.com/lit/an/sdya009c/sdya009c.pdf. TTL logic design

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  • \$\begingroup\$ I'm sure I've seen this same post recently and I'm sure you answered it for them then...dunno if it's the same poster under another name... Anyway, upvoting. \$\endgroup\$ – TonyM Apr 17 '17 at 17:37
  • \$\begingroup\$ he's a basic python coder \$\endgroup\$ – Sunnyskyguy EE75 Apr 17 '17 at 17:45
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Here is another NAND (any "0" in produces a "1" out_

schematic

simulate this circuit – Schematic created using CircuitLab

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