# How do you calculate the output voltage swing in an amplifier?

I have already calculated the DC values and the downswing of the circuit. I am not sure on how to calculate the no-load voltage upswing.

$$I_{C} = 4.416 mA$$ $$V_{E} = 5.3 V$$ $$V_{C} = 10V$$ $$V_{B} = 6V$$ $$A_{vo} = 0.995$$

My attempt:

$$V_{CE} = 0.3$$ $$(V_{C} + v_{c}) - (V_{E} + v_{e}) = 0.3$$ $$v_{c} = \frac{v_{o}}{A_{vo}}$$ $$v_{e} = v_{o}$$ $$\frac{v_{o}}{A_{vo}} -v_{o} = 0.3 -V_{C}+V_{E}$$ $$\frac{v_{o}}{0.995} -v_{o} = 0.3 -10+5.3$$ $$v_{o} = -845.6V$$

The answer should be $9.7V$.

• Where does "$V_{CE}=0.3$" come from? Apr 17, 2017 at 23:09
• It's given in the picture. It says, $V_{CE,Sat} = 0.3V$ Apr 17, 2017 at 23:13
• But this circuit should not be putting the bjt into saturation, so what does that have to do with anything? Apr 17, 2017 at 23:15
• Or is the actual question supposed to be "What is the maximum output swing of this circuit?" Apr 17, 2017 at 23:18
• Or possibly "What is the maximum output voltage of this circuit?" Apr 17, 2017 at 23:20

It looks like you mixed up the answer to a different question.

The output swing, assuming you operate the circuit within its linear regime, is just $$v_o = A_{vo}v_i$$ so $0.995v_i$. It can't be brought down to a numerical value since $v_i$ hasn't been specified.

The maximum output voltage (when operating linearly) is roughly $V_{CC}-V_{ce,sat}$, or 9.7 V. So it seems likely the question you were meant to answer is "What's the maximum output voltage of this circuit when operating linearly?"

If the circuit is kept in its linear range, the output voltage swing will be less than 9.7 V peak-peak, because the bias point puts the output slightly above the midpoint between ground and $V_{CC}-V_{ce,sat}$.

If the circuit is overdriven so that it clips on both the high and low swings, it could produce 9.7 V peak-peak output swing. However since there is no source impedance given for the input source, this would end up drawing large currents from the source in some parts of the cycle, so it isn't how you'd want to operate the circuit.

THIS CAN NEVER WORK for large swings. Since load cap will pull the emitter up at peak negative swings. Therefore Re must always be smaller than RL for small signals and <= 1/2 RL for full negative swing when AC coupled. Alternate improvement is a constant current sink for Re.

With a bias of Vb=6Vdc for Vcc=10V

• Ve min = 0V in theory ...!
• Ve max 9.7 with Vce(sat)=0.3 thus Vb= 10V-0.3 +Vbe= 10.4
• thus max swing is 9.7V with load fixed above

## Reality Check

For true linear operation with Vce (min)>=2V is a MUST, so max swing is 8V.

This is not for a switched operation where Vce=0.3V, you still use 2V min in order to get a sine positive peak equal to the negative peak within 1% to 0.1% depending on THD acceptable levels.

The exception is if linear operating currents are well below rated current.
This is due the less commonly specified $r_{CE}$ property of Vce saturation resistance which is shown in the slope of Vce vs Ic saturation curves and in tables by diodes Inc.

But with real transistors it is closer to V+-2V with a max swing of 8V due to saturation effects or rapid reduction in hFE starting below Vce=2V.

• "Therefore Re must always be smaller than RL for small signals and <= 1/2 RL for full negative swing when AC coupled". Surely that's not necessary. Even if RL is very low it will be linear for a small enough input swing. For large signals there is no fixed requirement for the ratio of Re to RL - you can never get full negative swing no matter how low Re is set. The negative limit is set by the current in the transistor going to zero. The optimum bias point is not necessarily at mid-rail - it will be somewhat higher. Apr 20, 2017 at 22:06