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I am designing nmos only LC VCO in cadence TSMC180. I have chosen the self-resonant frequency of the inductor to be twice the working frequency of the LC tank. Is it a proper design for LC tank? Or do I have to increase the SRF?

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  • \$\begingroup\$ What is the centre frequency and range you hope to achieve from your VCO? \$\endgroup\$ – Andy aka Apr 18 '17 at 12:18
  • \$\begingroup\$ The centre freq is 900MHz. The oscillator I designed was oscillating from 900MHz to 1.3GHz \$\endgroup\$ – Swap Apr 18 '17 at 12:50
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It's not possible to generalise, as it depends on what oscillator configuration you have chosen.

Twice the SRF means the effective shunt capacitance is 25% of the total you will need at the design frequency.

Some oscillator configurations will be quite tolerant of 25% of the tank capacitance being 'inaccessible' inside the inductor. If you want to apply the sustaining feedback by splitting the tank capacitance, then that may compromise how much intrinsic capacitance you can tolerate.

I suggest you simulate your proposed oscillator, first to see whether it runs, and then to see what margin there is before it doesn't. As long as there is reasonable margin, a fairly simple first order simulation should be adequate.

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Is it a proper design for LC tank?

It will work if the self-resonant-frequency (manifesting itself as extra capacitance in parallel with the varactor diode tuning) doesn't create a net capacitance that is too high at the highest DC control voltage.

So, work out the parasitic capacitance and add it to your varactor diode capacitance when controlled at the maximum DC voltage. Add also capacitance due to the PCB (maybe up to 1 pF) and calculate the oscillating frequency when the inductance is at its highest value (usually 10% high based on typical tolerances). If above 1.3 GHz then you should be OK.

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