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I've been wondering if its common and a good idea to combine a buck converter with a LDO to for example move 5V down to 1V for a microprocessor.

I'm unsure about the stability of the processor doing this, because I have no experience in using buck converters. However as my prototypes are getting smaller and smaller, heat dissipation is becoming a problem and this might be a solution.

Would it be a good idea to use a buck step-down converter to move 5V to something like 1.3V and do the last 300mV with a low noise high quality LDO?

How sensitive are microprocessors to ripple? Is it maybe even possible to only use a buck converter without compromising stability?

The microprocessor is being used as a part of the USB Audio decoding to I2S to the DAC, I know its a bad idea to use any kind of buck converter for analogue circuitry, so won't using a buck converter make ground more noisy and introduce noise to the audio signal?

Sorry for all the questions and thanks for you time!

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    \$\begingroup\$ For anyone looking at this topic again in the future, Buck converters are your best friend with power conversion. There are converters out there with extremely low ripple which will be more then enough for a microprocessor. For analogue circuitry you may still even use them in a Buck->LDO way and get very satisfying results! \$\endgroup\$ – Bart Aug 13 '18 at 19:15
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Lets put some numbers on "is well away from the (analog) devices that are noise sensitive"

enter image description here

Above is a simulation using default 14mm trace between sensor and Gain#1 (40db) and 14mm trace between Gain#1 and Gain#2 (34dB). Sensor provides 1 milliVoltPP. The OpAmps are OPA211 models (UGBW, Rnoise, Rout, DCgain) with 1nanoVolt noise density. With the selected Hfield aggressor (a switching regulator located 10mm away from the 2 traces of the PCB), we have only 2dB SNR. With Gargoyles off (that is, NONE of the 4 classes of interferers active), we have 54dB SNR.

What are your degrees-of-freedom? reduce the magnetic loop area (edit the trace to be shorter) or move the SwitchReg much further away or slow the SR edge rate (efficiency impairment). Here is the trace edit menu:

enter image description here

Some magnetic fields decay as 1/distance, some as 1/log(distance), some as 1/distance^2, etc. At 2MHz switcher clock rate, the PCB foil will attenuate the faster energy in the edges, but the 2MHz fundamental is little affected by Skin Depth. The OpAmps have enough UGBW to let lots of 2MHz energy come through.

EDIT At present, the prediction of HFI --- magnetic field interference --- by Signal Chain Explorer uses the infinite-wire-to-small-loop model: $$Vinduce = [MUo * MUr * Area/(2*pi*Distance)] * dI/dT$$

For air/vacuum/copper, this simplifies to $$2e-7*Area/Distance * dI/dT$$

A MCU clock line, swinging 5 volts in 5 nanoseconds while charging 20pF, needs current (I = C * dV/dt) of 20e-12 * 1v/1ns = 0.020 amps (probably 0.040 amps peak), with a triangular buildup and decay of current through all the MCU package and PCB inductances. What will 0.04 amps peak, rising in 2.5 nanoseconds, induce 1cm away into a 1cm^2 loop. (for easy math, use 2.0nS Trise)

Vinduce = 2e-7 * 0.01 meter * 0.01meter/0.01meter * 0.04amps/2nS

Vinduce = 2e-7 * 1e-2 * 1amp/50 nanoseconds (20amp/uS, or 20e6) = 2e-9 * 20e+6

Vinduce = 40e-3 = 40 milliVolts.

This decays only linearly with distance. However, the fast edge (2 or 2.5ns) should be strongly attenuated by any intervening copper sheets/planes, with skin depth being your friend.

Below is the HFI database (used if Gargoyles & HFI & I/C{enables trace model} are clicked); I've deselected the SwitchReg, and selected/saved the MCU clock.

enter image description here

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  • \$\begingroup\$ Thank you! The (non-ldo) power circuitry is located on a separate PCB that connects to the main PCB with a pin header which is located about 50mm from any analogue circuitry (Measured from point to point, ignoring space in between the power board floating above the mainboard) As opamps I'm using AD8599, which have a pretty high common mode rejection ratio. Using these opamps, and with that distence, I should be right and manage to get a final SNR of 110dB or more without issues if I'm not mistaken? Thanks again for your response \$\endgroup\$ – Bart Apr 19 '17 at 21:20
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It is common to follow up a buck (or boost) converter with an LDO to reduce ripple. You can even find chips that combine these two functions (buck and LDO).

Usually microcontrollers are okay with a few 10's of mV ripple, which is achievable with a buck alone (maybe with additional output filtering).

won't using a buck converter make ground more noisy and introduce noise to the audio signal?

This is an issue, but should be manageable if you make sure the return path for the (digital) devices powered by the high-ripple supply is well away from the (analog) devices that are noise-sensitive (assuming you're not trying to do 16-bit audio sampling or something).

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