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I need to program (in Verilog) a peripheral driver connected to an FPGA through 4 standard SPI pins. I have been trying to find an authoritative source that clearly specifies the timing diagrams for read and write requests, but nowhere quite found what I wanted.

Where can I find the timing diagrams needed to program a driver connected to an FPGA through SPI pins?

[Here is the datasheet of the peripheral I would like to communicate with through SPI. The SPI pins allow access to the configuration registers, in this case.]

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I've had the same problem in the past. It looks like there is no public spec available. Instead Motorola (SPI's originator) had timing diagrams in datasheets for controllers supporting SPI. For instance the 68HC11 datasheet has SPI timing information in section 10.17, on page 171. General SPI description on page 119 ff.

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"The SPI bus is broadly accepted because it has little or no patent issues. This is partly because Motorola, its creator, provides no specification or central support. Those applying SPI can create hardware and software solutions without patent issues, but also without support or definition of supporting protocols." (source)

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  • \$\begingroup\$ Thanks. So I understand how to make a 1-byte transfer (explained on page 121), but it's unclear to me what the more high-level timing diagram should be. For example, if I want to make a read request, how much latency is there between writing the address, and getting a response. \$\endgroup\$ – Randomblue Apr 17 '12 at 9:06
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    \$\begingroup\$ @Randomblue - That's a level up in your protocol, and isn't part of SPI. SPI is very low level, just shifting out and in data bits. \$\endgroup\$ – stevenvh Apr 17 '12 at 9:08
  • \$\begingroup\$ isn't that SPI is a universal ? \$\endgroup\$ – Standard Sandun Apr 17 '12 at 10:36
  • \$\begingroup\$ @sandun - Yes, IIRC Motorola never patented SPI, so everybody was free to adopt it. Which is what happened. \$\endgroup\$ – stevenvh Apr 17 '12 at 10:43
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The term "SPI" is applied to a variety of protocols. A typical SPI system will have one "master" device and one or more slaves. Each slave device will have a clock input, a data input, a data output, and typically a chip-select wire. A master device will have a clock output, data out, and data in, and will typically use a general-purpose I/O to drive slaves' chip-select wires. Generally, a slave-device's communications state machine will be held in reset any time its chip-select wire is deasserted.

There are so many variations that merely knowing something is "SPI" doesn't really say much about it. It's helpful to know that "MOSI" (master-out-slave-in) is a term used to describe both the master's data output and the slave's data input, and "MISO" (master-in-slave-out) is a term used to describe both the slave's data output and the master's data input. Otherwise, though, one really must consult an SPI device's data sheet to know how one will need to communicate with it. Most SPI peripherals found in microcontrollers can support the more common variations, but not all conrollers support all variations. For example, while most devices send and receive data most-significant-bit first, some devices send and receive data least-significant-bit first (and may have hardware reasons for doing so).

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