In a 2 layer PCB I routed some tracks under unused pins of a MCU to avoid GND polygon crossing, and also saved few vias. For example, using this trick 2 SDIO traces on the left were routed nicely together with other SDIO lines (and have a nice continuous GND on a bottom layer).
Assuming "standard" PCB/soldermask quality, how safe is to use this trick on volume production device (few thousand)?
I'm asking because I didn't see such routing in real-life products (did I invented new hack? :) and nothing on the Internet.
Unused GPIOs could be set to inputs and polled up/down internally, to be on a safe side if somehow soldermask is broken under them.