There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has positive clock, like this:
Question: why such flops are not the default flops that are used? Most CMOS libraries and designs are using posedge flops.
But, there are several advantages to master-flip flops that update their Q on negedge:
1. No headaches with hold timings, as D won't trigger on the posedge together with clock, making timing analysis simpler
2. No simulation shoot-through. If your design has clocking path longer than D path (for instance, there are clock gates), then the next stage will properly sample "previous" D value, instead of "currently updated" new one.
The only disadvantage I see is that you lose half a period of time for your combinational logic to settle.
Is there something else that I am missing?