There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has positive clock, like this: enter image description here

On the other hand, "usual" master slave flops have master on positive clock and slave on the negative clock, meaning they sample D on posedge and update their Q on negedge, like this one:
enter image description here

Question: why such flops are not the default flops that are used? Most CMOS libraries and designs are using posedge flops.

But, there are several advantages to master-flip flops that update their Q on negedge:
1. No headaches with hold timings, as D won't trigger on the posedge together with clock, making timing analysis simpler
2. No simulation shoot-through. If your design has clocking path longer than D path (for instance, there are clock gates), then the next stage will properly sample "previous" D value, instead of "currently updated" new one.
The only disadvantage I see is that you lose half a period of time for your combinational logic to settle.
Is there something else that I am missing?

  • \$\begingroup\$ Most people don't want to give up that disadvantage that you mention, and have the functionality of the part depend on the clock's positive and negative pulse widths. And you still have to worry about hold if the clock arrival times at every latch are not the same. \$\endgroup\$
    – stevesliva
    Jun 19, 2017 at 21:36

1 Answer 1


You are correct that master slave flip-flops provide the nice functionality that you define.

However there are other situations where you need that first latch on it's own.

For example, where the output of the second latch is dependent on some other input..


simulate this circuit – Schematic created using CircuitLab

As such you need the simple edge triggered latch as the primitive.

  • \$\begingroup\$ In this case you can use level latches to build that, right? But this still doesn't answer the question why only edge-triggered are overwhelmingly used in the designs (as primary library primitive), despite having simulation issues and hold timing headaches \$\endgroup\$ Apr 22, 2017 at 10:05
  • \$\begingroup\$ @artemonster the only have issues if you don't design it right. You need the primitive for the reasons mentioned above. It is always up to designer to use and time things properly. \$\endgroup\$
    – Trevor_G
    Apr 22, 2017 at 10:15
  • \$\begingroup\$ @artemonster the trick is to minimize the gate count and still stay synchronized. \$\endgroup\$
    – Trevor_G
    Apr 22, 2017 at 10:17
  • \$\begingroup\$ edge-triggered (sample and update on same clock edge) allow the rest of the clock cycle for combinatorial delays. \$\endgroup\$ Apr 22, 2017 at 13:32

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