The early Power Mosfets were deemed to be fully enhanced with 10 VDC between gate and source. The gate source threshold voltage was defined for 1mA drain current and would be between 2 and 4 VDC. The gate source rating was 20VDC but the curves showed that there was nothing to be gained by going over 10VDC.
Then logic level Fets arrived for 5VDC systems and then lower to interface with modern logic. The old school analog term called transconductance kept increasing as the on resistance went down every generation.
These days transconductance is not talked about in my neck of the woods because people think it is not important for switching applications. High transconductance and low gate volts are bad for switching when it comes to parasitics and EMC.
Sure the logic level fets do have a place. Some of my best friends use logic level fets. I avoid them because I do not want bad switching.
My question is why cant they make a fet that had a much thicker oxide layer and was fully enhanced at say 20VDC, had a gate source rating of say 40VDC and had a gate source threshold of say 4 to 8 VDC ?
Is their any upper limit of attainable gate voltage rating? Sure the gate capacitance would come down but how would we go on total gate energy?