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The early Power Mosfets were deemed to be fully enhanced with 10 VDC between gate and source. The gate source threshold voltage was defined for 1mA drain current and would be between 2 and 4 VDC. The gate source rating was 20VDC but the curves showed that there was nothing to be gained by going over 10VDC.

Then logic level Fets arrived for 5VDC systems and then lower to interface with modern logic. The old school analog term called transconductance kept increasing as the on resistance went down every generation.

These days transconductance is not talked about in my neck of the woods because people think it is not important for switching applications. High transconductance and low gate volts are bad for switching when it comes to parasitics and EMC.

Sure the logic level fets do have a place. Some of my best friends use logic level fets. I avoid them because I do not want bad switching.

My question is why cant they make a fet that had a much thicker oxide layer and was fully enhanced at say 20VDC, had a gate source rating of say 40VDC and had a gate source threshold of say 4 to 8 VDC ?

Is their any upper limit of attainable gate voltage rating? Sure the gate capacitance would come down but how would we go on total gate energy?

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    \$\begingroup\$ +1 very Interesting question - do you have a link for reading up on what you say: "High transconductance and low gate volts are bad for switching when it comes to parasitics and EMC"? \$\endgroup\$ – CL22 Apr 22 '17 at 11:21
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    \$\begingroup\$ @ Jodes .No link .I know it is bad by looking at lots of scope waveforms .Nowdays the currents are much higher and L dI/dT is much worse on the source inductance giving spikes that turn on low threshold gates during turnoff . \$\endgroup\$ – Autistic Apr 22 '17 at 11:27
  • \$\begingroup\$ Did you try newer leadless packages with very low source inductance? \$\endgroup\$ – peufeu Apr 22 '17 at 12:40
  • \$\begingroup\$ What packages are available for the GateDriver ICs? Also, some designers use lumped resistors between the GateDriver and the Power MOSFET, so the Cmiller will slow down the switching. \$\endgroup\$ – analogsystemsrf Apr 22 '17 at 13:26
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My question is why cant they make a fet that had a much thicker oxide layer and was fully enhanced at say 20VDC, had a gate source rating of say 40VDC and had a gate source threshold of say 4 to 8 VDC ?

There are some problems of having thicker oxides.

A) Thicker oxides have notoriously poorer quality than high quality "thin" thermal oxides. In particular, thicker oxides have a larger number of defects, and consequently the dielectric strength is reduced. Consequently, the gate breakdown voltage does not linearly scale with the oxide thickness. Therefore if you want to double the maximum voltage, you must use a more than double gate oxide thickness. A larger oxide means a smaller unit area gate capacitance (Cox, expressed in F/cm^2), i.e. a smaller drain current (and transconductance, as they are related). To recover the reduced Cox, you'll have to make your MOSFET with a larger channel width (W), compensating any benefit of a smaller gate capacitance Cg.

Furthermore, defects might act as hole/electron trapping centers, i.e. they will change the threshold voltage, over time, when charges are trapped.

B) Imagine you have a switching power supply. The power dissipated due to gate capacitance switching is Cg*Vgg^2*f, where f is the switching frequency, Vgg is the gate "On" voltage, and Cg is the gate capacitance. You want to double the oxide thickness, to have a double "ON" voltage. Therefore the capacitance will be Cg2= Cg/2, and the new voltage will be Vgg2 = 2*Vgg. Keeping a constant frequency, the power due to gate capacitance switching effectively doubles.

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  • In saturation region,it's small signal resistor,which is also called ro=1/gds.

    • It's usually designed to be very large because we want to get a large gain Av=gm*ro
  • In linear region,the resistance of a MOSFET is called RdsOn.

    • It's designed to be very small because we use MOSFET as a switch.

As the RdsOn gets smaller, the junction charge (Q=CV) and capacitance Ciss, Coss increases (unfortunately) and when switching causes slew rate limiting on the input and a surge current the gate drive during the Vgs threshold.

There are many other that determine size of the junction such as Pmax, Imax, Vdsmax, wafer technology, cost.

  • You probably want to look for Q*RdsOn product outliers below the trend.
  • Also most important now is the decoupling cap ESR over the entire spectrum of rise time up to 1/Tr to reduce conducted EMI and estimate the effects of your track or wire inductance for resonance frequency and Q.

enter image description here

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  • \$\begingroup\$ I'm interested in the data you used for this graph, since this is basically FETs sorted by figure of merit... \$\endgroup\$ – peufeu Aug 28 '17 at 19:20
  • \$\begingroup\$ I extracted all the PN from Digikey and plotted it. \$\endgroup\$ – Sunnyskyguy EE75 Aug 28 '17 at 19:29
  • \$\begingroup\$ Hehe, did you use the "download table" feature? I'll remember to use that in the future... \$\endgroup\$ – peufeu Aug 28 '17 at 19:34
  • \$\begingroup\$ yes with 500 results per download, in stock only \$\endgroup\$ – Sunnyskyguy EE75 Aug 28 '17 at 19:35

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