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Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-between them. There are several advantages to a latch-based design:

  1. Time borrowing: can relax timing a lot
  2. Reduced area and power consumption: you get the same logic with half of the registers

Disadvantages:

  1. Two-phase clocks with dead-time are necessary
  2. Hard to wrap your head around the concept
  3. Tools don't support the concept easily
  4. Hard to prototype. Every FPGA out there has a DFF in their cell, not a latch
  5. Hard to do a scan-chain

Are these disadvantages so severe that the latch designs were abandoned? I mean, if we had proper EDA tools and FPGAs we could still do it, right? Or am I missing something really important here?

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    \$\begingroup\$ Balancing both edges of a clock across the physical area and process variation is a nightmare. Single edge clock causes enough problems already. \$\endgroup\$ – Sean Houlihane Apr 22 '17 at 15:37
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    \$\begingroup\$ A modern flip-flop is not two latches squeezed together, it is an asynchronous state machine built to implement flip-flop bahavior. The master-slave designs you often see in teaching materials are not actually used. \$\endgroup\$ – Austin Apr 22 '17 at 19:29
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    \$\begingroup\$ @Austin I tend to disagree. if you lookup schematics of DFFs in common CMOS libraries you will find two latches (with one of the latching inverter being a transmission inverter) separated by 2 transmission gates with inverted clocks to each other \$\endgroup\$ – artemonster Apr 22 '17 at 20:20
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Your "advantages" don't hold water.

Modern synthesis tools can move logic around registers to optimize timing, so latches offer no advantage there.

How do you get "half the registers" by splitting them? Sounds like the same number of registers to me.

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  • \$\begingroup\$ Imagine a pipelined processor with 6 pipeline stages. That means, 6x stages of flip-flops, each containing two latches. In latch based design, you'll just have 3 stages for each high-phase and low-phase clock, thus having the half of total amount. But good point on register retiming, though. \$\endgroup\$ – artemonster Apr 22 '17 at 14:20
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    \$\begingroup\$ @artemonster A design requiring 6 pipeline stages is 6x18 levels of logic (or whatever). If you split this into high and low clock phases, you need 12x 9 levels of logic. More pipeline stages are added to increase clock speed, not because the architecture requires them. \$\endgroup\$ – Sean Houlihane Apr 22 '17 at 15:35
  • \$\begingroup\$ @SeanHoulihane I am sorry, the stackexchange glitched out on me so I can't upload the image directly, but please refer to this image: 2.bp.blogspot.com/-D-zIa3pSNcU/TZBTbYsUP_I/AAAAAAAAADI/… You have the same amount of pipeline stages and the same amount of logic in-between them, but you don't use "two latches" per stage to build a flop, but use 1 latch and two-phased clock. \$\endgroup\$ – artemonster Apr 22 '17 at 20:29
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I don't agree with your summary of what a DFF is. A DFF guarantees that the timing has to be related to only one event: the clock rising edge.

Your idea is to make totally asynchronous designs. Well... good luck with making timing closure with such a design. It would be a nightmare.

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  • \$\begingroup\$ eeeeeh, what? I've never spoken about async. designs. I mean latch based designs that are based on two-phase clocks. \$\endgroup\$ – artemonster Apr 22 '17 at 20:23

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