What are the “embedded” and “non-embedded” design flows?

Question

I'm reading the Spartan 6 user guide on the Memory Controller Block (MCB). The following quote discusses two design flows:

There are two supported design flows for the MCB:

1) Non-embedded design flow

• Conventional FPGA design with the Xilinx® ISE® tool flow
• MIG tool is used within the CORE Generator™ tool for MCB designs

2) Embedded design flow

• Processor-based FPGA system design with EDK tool flow
• IP Configurator in Xilinx Platform Studio (XPS) is used within the EDK environment for MCB designs

I'm not quite sure I understand the difference between the two design flows (despite the above "explanation"). What are the non-embedded and embedded design flows?

Answer 1

Embedded means "integral " or "deeply rooted" (adjective) In this case the noun is "design flows" specifically Xilinx's design flows.

Xilinx has some really big design bricks that are fee based IP circuits like {PLL with Phase Freq detector} or {RLL encoder/decoder} which saves you some grey cells late at nite at the expense of your boss's $ when it goes into production. So limit these choices to critical low volume usage or when there is no other choice.

Of course non-embedded means .. you are on your own baby...its a big chip with a matrix of inputs and outputs.

If that clears it up . score accordingly. Xilinx has some amazing library bricks in EDK but not free.... so cost of solution depends on your learning skills and experience.

Answer 2

The embedded design flow is for designs with a processor in the chip. This is typically the Xilinx MicroBlaze. That's why you need EDK; it is used to write software for the processor.

Answer 3

At its simplest:

Are you using/intending to connect the memory to a processor within in the FPGA? If so you want "embedded". Otherwise you are not embedded.

This can get more complex - if you have a processor, but are intending to share the memory between it and a custom block of HDL code that you write, then you are doing a bit of both. The way you solve it depends on things like how much control of the memory interface you need from your HDL code...