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I got the following text from lab work 2 of CMU's computer architecture course. I am actually trying to do this lab myself out of own interests and I am in no way a student of CMU.

The machine has a single-cycle microarchitecture: every instruction takes exactly one cycle to execute. Aside from correctness (as de ned by the architectural speci cations), this is the only constraint that we are placing on the machine's microarchitecture. As long as these two constraints are satis ed (i.e., correctness and single- cycle), you are free to implement the microarchitecture in anyway you want. To guide you along the way, we provide an abstract description of the single-cycle microarchitecture as we discussed in class.

  1. The architectural state of the machine (excluding memory) is stored in registers: the program counter and general-purpose registers
  2. There is a global wire called the \clock" that is connected to all the registers.
  3. When a register sees a rising edge on the clock, the register captures the instantaneous \snapshot" of the values on its input. From then on, the register holds the captured values and feeds them to its output.
  4. The output from the register(s) are fed into a combinational circuit consisting of logic gates (e.g., ADD). In turn, the output from the logic gates are fed back as input to the register(s).
  5. At the next rising edge on the clock, the register again captures the values on its input

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My doubt: It asks me to implement single cycle architecture but the points numbered from 1 to 5 doesn't seem to be single cycle.

Assume the instruction ADD R1, R2, R3. According to the steps from 1 to 5 this will take two clock cycles and not 1 clock cycle.

  • At the pos-edge of a clock cycle, the address (address in register file)registers R1 and R2 will be latched and the values in these registers will be sent to ALU for addition.

  • In the next pos-edge, the output of ALU will be written back to regiSter R3.

So it is actually taking two cycle right? EThen why is it called as single cycle instruction?

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    \$\begingroup\$ If you look at it, you might make the case that 1 instruction takes 2 cycles to appear at the ouput, however if you do multiple instructions, it's effectively 1 cycle per instruction, i.e. 10 instructions takes 11 cycles, 100 instructions takes 101 cycles. \$\endgroup\$
    – BeB00
    Apr 23 '17 at 17:40
  • \$\begingroup\$ YOu have to make your ALU calculate the result within the same clock cycle so that it is written to R3 in the same clock cycle, too. Only then you've reached single-cycle execution. (i.e. while @BeB00's considerations are interesting, they are irrelevant) \$\endgroup\$ Apr 23 '17 at 17:42
  • \$\begingroup\$ Actually, even that isnt really the case. You can never directly look at the contents of any register, only try to read the contents through a read instruction. If you activate your add instruction, clock the cpu one time, then activate your read instruction, and clock the cpu one time, you will get the correct result. edit: this is a reply to my previous comment \$\endgroup\$
    – BeB00
    Apr 23 '17 at 17:42
  • \$\begingroup\$ @BeB00 that would be a three-cycle instruction. \$\endgroup\$ Apr 23 '17 at 17:43
  • \$\begingroup\$ @MarcusMüller When i say activate, i mean have the relevant opcode in the control circuitry \$\endgroup\$
    – BeB00
    Apr 23 '17 at 17:44
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The only way I know to make read and write happen in the same clock cycle is for register reads to be triggered on positive edge and register writes to be triggered on negative edge(or vice versa), and then to make it so that your data path logic fully propagates within a half clock period. In a single cycle architecture, it's really just a semantic difference, a bit of trickery.

In more sophisticated clocking schemes, you might actually have multiple clock phases, so the 'edge triggering' relationship need not be symmetric as I've described it. When your core is pipelined, this actually matters for correctness purposes so that you don't have a race between your register read and writeback stages.

I think you are justified in being confused about how reads and writes are related in the register file, but that requires you to dig a bit deeper into the transistor level implementation of a single-bit register. I think you will find that there is a race if both events (read and write) are triggered by the same clock edge and your combinational logic can propagate a change before the register state is fully latched. Have a look at this webpage for a logical deconstruction of an edge triggered D flip flop.

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Warning: single cycle instruction may be a marketing move.

Consider the datasheet for PIC18F4xK22.

At most noticeable places you see the following:

All instructions are single cycle, except for any program branches

Sounds cool? But buried somewhere in the doc you see the following:

An “Instruction Cycle” consists of four Q cycles: Q1 through Q4.

Thus in reality your instruction executes 4 system clocks.

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I said this in the comments, but it's a bit fragmented.

Basically, you are correct that it would take two clock cycles to run an ADD instruction and then latch it into a register.

However, when you run the next instruction, this latches the previous result into the register, so if you run two ADD's back to back, you will get the correct result and it will only take two cycles.

As a sort of aside, having a result latched into a register is only relevant if you want to run an instruction on it. If the last command in your code was an ADD, and you didn't clock again after that, the registers would not contain the latest result, but it doesnt matter because you dont read them again. As soon as you ran an instruction again to read them, they would latch and then your instruction would run, giving the correct result.

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  • \$\begingroup\$ One way to avoid this kind of thing would be to have the registers latch on the falling edge, but this would limit your speed by half, and not be very useful \$\endgroup\$
    – BeB00
    Apr 23 '17 at 17:59
  • \$\begingroup\$ You have said two back to back ADD will take 2 clock cyles. Won't it be 3? Say we have ADD R1, R2, R3 and then ADD R4, R5, R6. In pos-edge 1, R1 and R2 will be read. In pos-edge 2, R3 will be written back and R4 and R5 will be read. In pos-edge 3, R3 of second instruction will be written back. Am I corect? (don't mind the result of first add being not used and overwritten by next instruction in this example) \$\endgroup\$
    – Jsmith
    Apr 23 '17 at 18:12
  • \$\begingroup\$ Yes, but it's still considered 2 cycles. That third cycle, where the writeback is happening, can be any instruction, including NOP. If you wrote a program that was 10 instructions long, whatever those instructons were, the program would run correctly and completely if you clocked the processor 10 times. \$\endgroup\$
    – BeB00
    Apr 23 '17 at 18:15
  • \$\begingroup\$ Okay I understand, then what about trying to read R3 immediately after writing R3? I mean something like ADD R1, R2, R3 and then ADD R3, R3, R3. There will be problem when R3 is read before/or while R3 from previous ADD is being written right? \$\endgroup\$
    – Jsmith
    Apr 23 '17 at 18:18
  • \$\begingroup\$ So when we want to read R3 after ADD R1, R2, R3, we have to include a NOP in between otherwise it is a bug? \$\endgroup\$
    – Jsmith
    Apr 23 '17 at 18:21
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Its a single cycle architecture! When the add r1,r2,r3 comes into the combinational decoder it decodes the message and tells the ALU to do addition of r1,r2 and the result is an input to register r3. Now the value of addition can be written back at the next rising clock edge or at the falling edge(preferred). As write back does not affects the decoder part of micro architecture next inxtruction will be decoded and so on. Hope it helps.

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no reason why you cant implement this in a single cycle, at the beginning of the cycle the registers output their current value, your instruction decoder sees and add, sees the in put registers and combinationally produces the sum of those items, it also sees the destination and combinatinally feeds the result into the input to r3 on the rising edge that ends this single cycle r3 gets the sum of r1 and r2. No reason to use a falling edge or anything like that.

Now had the registers been in a register file then yes you have a much bigger problem, you cant read the two inputs in a single clock without changing the definition of a clock (using the falling edge is cheating that just changes the definition of one clock into two clocks).

with the registers being separate from each other with their own input and output and not counting memory (at times you can still do this as well) you can easily make a single cycle machine. the beginning of the cycle the register outputs are ready, combinationally you compute the register inputs before the end of the cycle.

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If registers are tri-state coupled to busA and busB as soon as the opcodes are decoded, and those internal buses route the operands to ALU, with the ALU function being selected from that tiny part of the instructon code, and the destination register has the ALU output presented to that register's input pins, then the next clock cycle (all clocking actions occurning MCU-wide on the same edge), then you have a single-clock-cycle MCU.

Its up to you to define the tristate behaviors to implement this.

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