You seem to be describing a circuit that, when driven logic high, produces a logic high that changes back to logic low shortly after.
If this is true...
That would be a positive edge triggered monostable. You can implement a simple one like this:
simulate this circuit – Schematic created using CircuitLab
(You haven't say if you're using TTL (5 V) or LVTTL (3.3 V) or something else so I'll use TTL in the explanations here and use perfect 5 V/0 V outputs.)
Let's start with (Vin = 0 V) and C1 discharged. When Vin goes to logic high (5 V), C1 has no charge across its plates so Vout instantaneously goes to 5 V. C1 starts to charge through R1, producing an exponential voltage across its plates. Vout accordingly decays from 5 V to 0 V exponentially, crossing from good logic high min. (2 V) to good logic low max. (0.8 V) on the way. The minimum time that your logic high pulse exists on Vout for can be derived from the charging equation for a capacitor: the time to charge from 0 V to 3 V, which causes Vout to drop from 5 V to 2 V. You can choose C1 and R1 values from that.
When Vin goes logic low, C1 will be charged to 5 V so Vout will be instantaneously taken to -5 V, then start to discharge towards 0 V through R1. To prevent this negative pulse from damaging the next logic gate, D1 clamps Vout from going any lower than about -0.2 V by fast-discharging C1.
Remember that the value of R1 must be chosen to limit the current into C1 to a suitably small value that the driving logic gate can provide. I would suggest keeping it to 500 uA or less. Do not make the current so small that the input leakage current of the next gate (+/-10 uA for 1xHCT) will start to have a significant effect. Keep it above 100 uA and you should be OK.
Incidentally, I've shown C1 as 47 nF just as a guide value, to stop people thinking of 10 uF or something. Put in the value you calculate.
This circuit is OK for fast pulses, maybe less than 10 us or so.
If pulse is to be much longer, the C1 charging slope becomes so long that the logic gate on Vout spends to long in the indeterminate logic zone, here between 0.8 V and 2 V, for a reliably noise-free output. In that case, it is better to use a dedicated monostable IC or a gate with a Schmitt trigger input on Vout in a circuit such as this:
simulate this circuit
The RC circuit principle is the same as for the first circuit but inverted. At rest, C1 is discharged with both plates at 5 V. When the input inverter is driven high, its output goes low and Vc instantaneously goes low, switching the output inverter high. C1 charges towards 5 V (Vdd) and when it crosses the positive-going threshold for the output Schmitt inverter, that inverter goes low, ending the brief output pulse. D1 does the same job, clamping the C1 voltage to 5.2 V or so when the input inverter drives 5 V out to the capacitor.
You could look at the 74HCT14 hex Schmitt inverter or whatever suits your logic family. The 74HCT14 input thresholds are around 1.1 V for positive-going and 0.9 V for negative-going. So your minimum output pulse would be approximately the time for C1 to charge from 0 V to 1.1 V.
If the pulse is to be tens of ms, this circuit's inaccuracy may become too much of a factor, depending on your application. It's then time to look at a more exact circuit such as a dedicated monostable IC or a digital solution with a counter. It just depends what fits your application, reliability and design cost/time budgets best.