This is the phase frequency detector circuit that I am using in my pll design. How do I find the gain of the PFD when all the blocks are digital and the input and output waveforms are pulse waveforms?

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    \$\begingroup\$ The gain is defined by the push-pull analogue current sources attached to the digital outputs. You don't show these and neither do you show the loop filter so no, there can be no gain associated with just what you show. You might also consider formally accepting answers to questions you have raised that have proven useful to you. Call it "the fee" for getting good advice. \$\endgroup\$ – Andy aka Apr 24 '17 at 12:39
  • \$\begingroup\$ To obtain full swing output UP/DOWN pulses, and perhaps widen those pulses to what a analog circuit (the Charge Pump) needs, insert some delay between NAND output and RST pins. If you want the lowest jitter/phasenoise, then design that delay for low thermal noise and low deterministic trash. \$\endgroup\$ – analogsystemsrf Apr 24 '17 at 14:50

The gain will be quoted as 'output per radian' or 'output per cycle'. We usually use the former as it's more natural for loop bandwidth calculations, but it's easier to calculate the latter from the PSD.

Consider what happens when one input lags the other by 0.1 cycles. The output will be active for 0.1 of a cycle, per cycle. In other words, the output will be active with a duty cycle of the phase difference in cycles.

If your output logic switches 5v, then the output gain is 5v per cycle, about 0.8v per radian. If your logic switches 5mA current sources, then your gain is 5mA per cycle, or 800uA per radian.

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