I'm reading the datasheet for the NCP81151B-D MOSFET gate driver / half bridge. It has a standard bootstrap configuration where the switched note (drain + source of the totem pole N-FETs) is tied through a diode and acts as a charge pump to provide drive voltage for the high-side FET.

What I don't understand is this specification:

BST Bootstrap Supply Voltage
35 V wrt/ GND
40 V 50 ns wrt/ GND
6.5 V wrt/ SW
7.7 V < 50 ns wrt/ SW
−0.3 V wrt/SW

(taken from http://www.onsemi.com/pub/Collateral/NCP81151B-D.PDF )

Consider switching a 20V load.

When the gate driver is in the low-on configuration, the SW node would presumably be close to GND, but that means that the SW/BST voltage difference will be 20V minus whatever charge voltage is built up in the capacitor. This will clearly be higher than 7.7V by a rather large margin when the capacitor is empty.

The only way these specifications would make sense for the application, in my mind, is if the maximum voltage was the HIGHER of (SW + 6.5V) or (35V.) However, it doesn't specify that in the data sheet, and thus my engineering reading of this is "the device will fail if you exceed either of these voltages."

How should I know what the correct reading is? ONSemi doesn't list a mail address in their contact section. Has anyone used this part and know for sure that the "higher of" reading is correct?

Diagram of the NCP81151B-D

Table of maximum ratings for NCP81151B-D


1 Answer 1


When the low side FET is turned on, the SW node voltage will be close to ground as you stated. The bootstrap capacitor, connected between the SW node and the BST node, will then be charged up to about Vcc - V_diode. Once you release the low-side mosfet, the bootstrap capacitor will be "floating" on the SW node, but the BST node voltage with regards to SW will still be whatever the charge built-up during the low side on time.

  • \$\begingroup\$ I understand how the charge pump works. My question is: When the capacitor is charged to Vcc - V_diode, and then SW goes to Vcc, then BST will be at (2 * Vcc - V_diode) The chip is rated for 35V Vcc, but it seems to only be effective up to 17V or so because 2*35V-0.4V is > 69V. Or maybe they suggest that I put a Zener between VCC and BST to make sure that BST is no higher than SW+6.5V? And, if so, is the maximum effective Vcc really (35V-6.5V=28.5V) ? \$\endgroup\$
    – Jon Watte
    Apr 24, 2017 at 19:30
  • \$\begingroup\$ Additionally, even when SW is low, once the capacitor is charged, the BST voltage will be at Vcc - V_diode, which is a much higher voltage than SW + 6.5V. (This is the better-explained half of my original question.) I don't understand why they put in the BST-SW voltage specification -- what does this mean, and what am I supposed to do with this? \$\endgroup\$
    – Jon Watte
    Apr 24, 2017 at 19:36
  • 1
    \$\begingroup\$ Be aware that Vcc in your application will probably be around 5 V. The first line in the absolute maximum rating specifies a maximum Vcc of 6.5 V. So your bootstrap capacitor will be Charged to say 5 V. This respects the 6.5 V wrt/ SW. Your load voltage (let's call it V_load)is the 20 V you mentioned earlier. Do not apply 20 V to the Vcc node or you'll burn your driver. Once you release the low side and turn on the high side, your BST node will rise to V_load + Vcc - Vdiode. This should respect the 35 V wrt/ GND. You can then deduce that your maximum V_load should be around 30 V for a 5 V Vcc. \$\endgroup\$ Apr 25, 2017 at 14:04
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    \$\begingroup\$ Oh, that's what I was missing! Vcc, not Vload! The other gate drivers I've been using have all used floating high ends where you bootstrap from the Vload, not Vcc. That makes more sense now. \$\endgroup\$
    – Jon Watte
    Apr 25, 2017 at 20:11

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