From my understanding this reduces the functionality of the JK flip flop to that of a D type flip flop, so why not just use D-type flip flops? I've seen SIPO shift registers constructed form D type flip flops and not JK ones, so I'm a little confused why this seems to be convention.
For some reason, device based on D flops have largely standardized on using the rising clock edge as the capture/output event, but JK flip flops have standardized on using the falling edge. If a ripple counter is supposed to count upward, each bit should change its state on the falling edge of the previous bit, and so using JK flops makes it possible to build an up-counting ripple counter where the data output of each stage can be fed to the next stage.
I personally think it would have been helpful to have a wider range of devices that are based on D-style flops operate on the falling edge rather than the rising edge, but for whatever reason JK flops are just about the only common "jelly-bean" logic chip that uses the falling edge.