Everywhere I encounter either asyncronous (ripple counter) binary counters or syncronous ones, the application uses JK flip flops with the J and K inputs tied together, such as described here: enter image description here

From my understanding this reduces the functionality of the JK flip flop to that of a D type flip flop, so why not just use D-type flip flops? I've seen SIPO shift registers constructed form D type flip flops and not JK ones, so I'm a little confused why this seems to be convention.

  • \$\begingroup\$ JK flip-flops toggle when J=1 and K=1. if you were to build a counter outa D flip-flops, you would need a full binary adder for each bit. \$\endgroup\$ Commented Apr 24, 2017 at 18:58
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    \$\begingroup\$ JK with inputs tied together is a T-Type not a D-Type. \$\endgroup\$
    – Trevor_G
    Commented Apr 24, 2017 at 19:18
  • \$\begingroup\$ @Trevor my mistake, I guess the question still holds for why JK instead of T type though? \$\endgroup\$
    – Alex
    Commented Apr 24, 2017 at 19:21
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    \$\begingroup\$ I think part of the reason is just availability. Because JK flip flops can be configured to act as RS, D, or T flip flops, there's really no reason to mass-produce the other types (save for simplicity, but with modern technology, at least for discrete flip flop ICs, it doesn't really cost any more to add a few transistors). \$\endgroup\$
    – Hearth
    Commented Apr 24, 2017 at 21:32
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    \$\begingroup\$ @Felthry: If a D flop has an inverted output available, it's easy to configure it to flip state on every clock edge. The "problem" is that D flops react to rising edges, but each bit of an up counter should increment on the falling edge of the previous one. \$\endgroup\$
    – supercat
    Commented Apr 24, 2017 at 22:55

1 Answer 1


For some reason, device based on D flops have largely standardized on using the rising clock edge as the capture/output event, but JK flip flops have standardized on using the falling edge. If a ripple counter is supposed to count upward, each bit should change its state on the falling edge of the previous bit, and so using JK flops makes it possible to build an up-counting ripple counter where the data output of each stage can be fed to the next stage.

I personally think it would have been helpful to have a wider range of devices that are based on D-style flops operate on the falling edge rather than the rising edge, but for whatever reason JK flops are just about the only common "jelly-bean" logic chip that uses the falling edge.


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