Starting with JK flip-flop, show the design of a D flip-flop with a synchronous reset, R.

I know how to create a D flip flop with J-K flip flop, but i'm not sure what "synchronous reset, R" exactly means. Is it another input in D flip flop that resets output when is active? And what's the point of it?


A reset is an additional signal input for the flip-flop, generally with a higher priority than the other inputs, that (when active) set the flip-flop output to logic value 0.

A synchronous reset is a reset signal that operates synchronously with the clock. In other words, if RESET = 1 when the D flip-flop receives a clock edge, the output will be set to logic value 0, no matter what the DATA input is.

A reset signal is very common. For example, when you have any kind of register that currently holds a number (an accumulator, a general register) and you want to make sure that the stored value is erased before using it again. A reset signal is the easiest way to achieve this. The same reset signal could also be shared among multiple registers to reset the state of a more complicated logic (a Finite State Machine for example).

  • \$\begingroup\$ Sync Reset D FF's do not exist in discrete IC's . That is simply an AND gated input for RESET = LO on next clk. that may be designed in a CPLD or FSM \$\endgroup\$ – Sunnyskyguy EE75 Apr 9 at 17:15

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