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I have a question about DDR4 training sequence, and hope someone can give me some information.

As I know, there will be training sequence at system boot. (In my system, it's called 1D/2D training, I'm not sure if that's a standard term or it's the specific term for this controller).

My understanding is, the controller will get a "working condition" through this training process (the working condition is a suitable Vref and RD/WR timing).

Is that a standard procedure for all the DDR4 DIMM?

How do I train a DDR4 memory module?

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There isn't a standard procedure defined; JEDEC says its up to each manufacturer to determine the most appropriate way to carry it out. But there is a guidance document produced by Micron that gives you a good overview of the process.

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As @Finbarr mentioned, there is no standard procedure. As per JEDEC standard, MC will support feature but they are not mandatory. For DDR4, there will be Read Leveling, Write Leveling and Vref Training. There can be quite many additional trainings too. MC needs to provide support for these trainings, but are not required to be performed. For eg. If you can find perfect DQ, DQS delay then you don't need to train them explicitly.

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