Power-on Reset for CD4017 gives unexpected results

Question

In the circuit below, a 555 timer produces approximately 1 pulse per second, and the CD4017 counts pulses. The initial state of a CD4017 is undefined, thus I need a reset pulse on power up. In the circuit, that is a 4.7uF capacitor between Vdd and the Reset pin, and a 10k resistor from the Reset pin to ground.
As I understand it, when the power is first applied, the capacitor has no charge. Until charged, it has effectively zero resistance, causing the Reset pin to go HI. Then it charges, giving it high resistance, and the 10k resistor pulls the Reset pin LO.

That's the theory, anyway, according to various circuits I have studied around on other sites. Since it is used a lot, I assumed it was a standard technique.

But what I see in practice is:

1. Turning on the power when the circuit and power supply has been turned off for awhile causes the Q0 LED to light briefly, then it quickly jumps to Q1.
2. If the power has been on, then I quickly turn it off then back on, the Q0 LED lights for a full second, then Q1 lights, the way I want it to always work.

Confession: the indicator LEDs are not actually as I have drawn them above. I prototyped this circuit on a PAD-234A, which has eight buffered LEDs, and I just used those. One buffered LED circuit (from the PAD-234A schematic) is as follows:

Any ideas on why I see this behavior? Is there a better power-on reset for a CD4017?

Answer 1

The 4017 is clocked on the rising edge, and you have the clock line high when it comes out of reset.

Try connecting clock in to Vdd and the 555 output to inhibit in. Inhibit is just an inverted clock input (sans Schmitt trigger). Or add an inverter between 555 and clock in.

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In general this is a really crummy reset circuit - criminally bad for anything important. Use a reset (supervisor) chip that provides a sharp fixed-length reset pulse out (eg. 200ms) and also detects slow brownouts and slow Vdd rise. They are plentiful and cheap, and designing one that is bulletproof is non-trivial.

If you insist on using this circuit, at least add a few K resistor in series with the reset input. Otherwise shorting or putting a heavy load turning Vdd off could damage the chip by discharging the 4.7uF through the input protection diodes.

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Edit: Rough schematic showing supervisor chip ADM803/ADX803, you may want to add a power-on LED or resistor from Vdd to GND to help discharge the 5V faster so it resets reliably on a short power interruption.

Answer 2

There are three issues with this circuit.

1. The RC time constant of the reset circuit is just under half the cycle time of the 555, which, because of issue #2, is clocking the counter almost as soon as it comes out of reset. As such, your reset time is far too long. A 0.1uF capacitor would give you an RC of about 1mS which is totally sufficient for your purpose.

2. The clock signal is actually inverted. That is the first clock pulse arrives half a second after power on, not the full second you expect. You could fix that with an invertor, or you could pull a trick on the CD4017 by feeding the clock into the \$\overline{CLOCK-INHIBIT}\$ line and tieing the \$CLOCK\$ line high.

3. As you discovered by pulsing the power, You have no circuitry to discharge those caps when that event occurs. It would be prudent to add diodes, pointing up, from Vdd to a.) the top of the 10uF 555 Capacitor, and B.) to the reset pin of the counter.