clock oscillator substitution, jitter question (audio DAC)

Question

I need a 5 x 7 mm HCMOS clock oscillator for my hifi audio DAC (Texas Instruments PCM5122)

I used to employ the following oscillator: FXO-HC736R-22.5792, but it is now discontinued, and the suggested replacement is currently not available from my preferred distributor (Mouser).

I think I may be able to substitute it with one of these:

1. KC7050K22.5792C1GE00
2. C3391-22.5792
3. DSC1001CI2-022.5792T

but I'm not able to compare the specs related to jitter/phase noise. Can anyone help me understand how these replacements could perform, compared to the "original"?

Answer 1

Read this.

• "DSC1001 is a silicon MEMS based CMOS oscillator offering excellent jitter and stability performance"

Forget it. It's a MEMS oscillator, not a XO, thus audio band phase noise will be horrendous. It only specifies cycle to cycle jitter, not period jitter, which is a tell tale.

• FOX XPresso uses an internal fractional PLL.

This is awesome, because they actually only stock one model and it can be programmed at the factory to give any frequency you want... but the phase noise graph isn't as pretty as a real XO.

• Crystek C3XX specifies "Jitter RMS: 12 kHz~80 MHz" which is a much more useful spec than cycle-to-cycle!

It is the RMS jitter based on phase noise integrated over the specified bandwidth. Unfortunately, for audio you'd need it specced lower than 12k, but it's a start.

• The Kyocera one has similar specs, but they also give phase noise depending on frequency.

So you can enter the values in a conversion tool to have an idea of your RMS jitter over the audio band. Unfortunately, since Crystek does not give the phase noise values, you cannot compare the two.

Among your list, I'm voting for Kyocera or Crystek, then.

I'll put on my audiophile hat for a second: we did some blind tests on $1-2 canned clocks, and did hear quite a bit of difference between them. XPresso was one of the worst. My fave is Vectron VCC1 which is not available in your frequency. Results correlate with phase noise/jitter which I did measure also. No tests were done on expensive clocks mind you, this was just a fun experiment, and I'm not audiophile enough to use a clock worth 20x more than the dac chip, thank you very much!!!

Now, as pointed out by analogsystemsrf (he knows what he's talking about)...

• Supply noise on your oscillator will wiggle its frequency. In terms of phase noise, this means the oscillator integrates supply noise into phase noise. Thus a noisy supply will destroy lowish-frequency phase noise performance (ie, audio). So please don't power the damn thing from your MCU's 3V3 rail, I mean at least invest $1.5 into an ADP151 or a LP2985, ferrite beads, and some caps...

• Noise picked up on the clock trace (or the GND, always mind the GND) between clock and DAC also counts, but it is not integrated, therefore problems are easier to avoid unless your layout is criminally bad (like no continuous ground plane under all the high speed stuff... or the clock goes through a ribbon cable next to the DATA line... huge crosstalk... or there's a switcher in the vicinity).

• Noise on DAC DVCC modulates its clock input gate voltage threshold and also adds jitter, so don't blindly connect it to a noisy DVCC...

Also if you use a sigma delta DAC high freq jitter also matters: the noise shaper makes huge efforts to push quantization noise into HF... and then HF clock jitter can fold that noise back into the audio band.

Note that many things other than jitter influence dac performance, but a reasonably low jitter is surprisingly easy to get right, so there is no reason to screw it up: good layout, good grounding, clean supplies... and the rest of the design also benefits from this.

(by "reasonably" I mean... you know, reasonably low, not down to bullshitium levels)

Answer 2

In reconstructing audio, all the jitter ends up (folded down) in the half-reconstruction-clock bandwidth. Tones (e.g 60Hz, or 120Hz, or 2MHz SwitchRg VDD trash in power to the oscillator, or FPGA VDDringing at 300MHz that magnetically couples to oscillator edges) all end up in the half-reconstruction-clock bandwidth.

Suppose Fclk is 50KHz, with period of 20uS, or 20,000 nanoseconds or 20,000,000 picoseconds. For 1ppm jitter, you need approximately 20 picoseconds jitter. I'm ignoring a factor of PI in this math.

Assume your clock generator produces square wave with 1 volt/nanosecond edge rate. What amplitude of trash can be tolerated on the edge, specifically near the zero-crossing or the logic-switching threshold?

Tj = Vnoise/SlewRate, thus Vnoise = Tj * SlewRate

The allowed Vnoise is 20pS * 1 Billion volts/second = 20e-12 * 1e+9 = 20e-3

Your budget is 0.02 volts total trash coupled onto that edge. At ANY point up to the reconstruction DAC switching edges inside the TI DAC.

edit

Note the requirement for 1 Billion volts/second slewrate in the clock signal. Is that easy to meet? No. Lets examine a 10MHz crystal oscillator with 2 voltsPP amplitude. The slew rate is 10MHz * 1 * pi * (2voltpp/2) = 63 volt/microsecond. Our Slewrate dropped from 1Billlion to 63Million, thus the noise needs to also drop, from 0.02volts to 0.02 * 63/1000 = 0.02 * 0.063 = 0.0012 volts, or 1,200 microvolts noise.

Thus the circuitry, converting the 10MHz sinusoid into a 10MHz squarewave, can only tolerate 1,200 microvolts noise on the VDD supply. (most schmidts have poor power-supply-rejection 0dB or 6dB; we'll assume 0dB)

Are you attentive to the VDD on the internal circuitry having function of amplifying/squaring the crystal sinwave?

Answer 3

Since you're only dealing with audio here, you can safely ignore the jitter specs. All of these have jitter on the order of a few to a few dozen picoseconds, which is far, far better than any audio application should ever need.

Answer 4

You should first figure out what the input clock jitter requirement is from TI's DAC data sheet or factory phone call. Then, try to find an oscillator that can meet it.

According to the Audio Engineering Society (AES) standard [1], you'll want to analyze "baseband jitter" from 100 Hz to 40 kHz. This can be interpreted as basically phase noise at offset frequencies from 100 Hz to 40 kHz. The lower the phase noise, the better (but remember, you only care about that offset frequency range, so don't pay for more performance than you need).

One complication is the DAC may pass your clock through an internal PLL. If so, you'd want to know the jitter transfer function of that PLL and model its affect on the phase noise (for example, using an online phase noise calculator, such as https://www.jitterlabs.com/support/calculators).

As you learned, each clock mfgr reports jitter/phase noise differently. Thus, it's very hard to compare datasheets. You can request the clock manufacturer to perform custom measurements for your application, or buy samples and perform your own measurements, or outsource it to an independent lab.

[1] "AES Information Document for digital audio measurements - jitter performance specifications," AES-12id-2006 (r2011), printed 10/15/2011 by Audio Engineering Society, Inc.