Here's one thats been puzzling me for a while.

I have an FPGA design in Altera, driving an audio chip and programmed through its serial interface. I monitor and debug this with an oscilloscope/SignalTAP. The chip is set to a loopback configuration so that whatever is played into LineIn comes out LineOut.

The audio chip schematic is shown below, and shows the I2C_SDAT and I2C_SCL interface pins. Of the inputs, AUD_XCK is provided by an IP clock generator (standard audio ~44 kHz) and AUD_DACDAT is tied to AUD_ADCDAT to create the loopback by connecting the ADC straight to the DAC.

Looking at some of the clocks, the AUD_BCLK (bit rate clock), AUD_DACLRCK and AUD_ADCLRCK (ADC & DAC sample rate clocks) are all generated internally (in what the datasheet calls "master" mode). They are not needed as the digital data from the ADC is fed straight back to the DAC output to go to LineOut.

enter image description here

However! When programming the serial I2C bus I had anomalous behaviour. The bus would program the chip correctly (all ACK's present). However - the ADC-DAC loopback did not function at all. My first thought was that I was failing to program the interface correctly.

After much gnashing of teeth, I stopped scrutinising my I2C (which after all, was being ACK'd by the chip). In order to see if the AUD_BCLK and other clocks were functioning in the logic analyzer, I had to add them to the design - and the very act of doing so made it all start working, even though they were left unconnected as shown below:

enter image description here

I found that simply by including these unconnected clocks made the difference between the chip functioning or not. I'm looking for ideas as to what the Altera tool does to unreferenced pins in the design so that not including the BCLK, DACLRCK/ADCLRCK clocks in the logical design stops the chip working, even though they are logically unconnected! Does Altera tie all unused pins to ground when it abstracts them away or similar?

Sorry for the longer post - I'm hoping that I've managed to explain the scenario, all ideas/recommendations are welcome!


  • \$\begingroup\$ I believe there is a setting under Settings somewhere to configure default unused pin function. \$\endgroup\$ – Trevor_G Apr 27 '17 at 20:19
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    \$\begingroup\$ Generally unused pins remain as high-z inputs. No idea why it would make a difference whether they are defined or not. \$\endgroup\$ – Tom Carpenter Apr 27 '17 at 20:42

By default, Quartus II used to set unused pins as outputs driving low. This wasn't good as you can imagine - one wrong pin constraint and a used input pin could be wrongly considered unused and be driving a shorting low onto the input signal.

In more recent versions, it was changed to the sensible 'as input tri-stated with weak pull-up', which saved me having to go and change it to this every time I created a new project.

You can change it in Assignments/Device/DeviceAndPinOptions/UnusedPins, which bring up the below dialogue box:

enter image description here

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    \$\begingroup\$ Had to change some of the badly thought accidental race conditions in my design that this change brought to light, but it was nevertheless the solution! \$\endgroup\$ – davidhood2 Apr 28 '17 at 15:22
  • \$\begingroup\$ Do you remember when this change happened? I have been using altera FPGAs for over a decade and I can't recall a time before this change, but I may not have been paying attention in the early years. \$\endgroup\$ – Peter Green Nov 21 '19 at 9:54
  • \$\begingroup\$ @PeterGreen, the most recent I can recall was 2007 when I found that problem once again, for a client in someone else's design. The client was probably using a Quartus pre-dating then but might have been the latest one. I first used Quartus in 1999 when it was newly-out and a bug-ridden crashing pain, taking 5 hours to synthesize for a 20KE. Quartus II came along less than a year later, I think, and was stable, quicker and usable. After that it was versions of Quartus II. \$\endgroup\$ – TonyM Nov 21 '19 at 19:06

In modern versions of Quartus the default for unused pins is "input with weak pull-up"*, this is also the state the pins will be in before the FPGA is programmed. I presume this default was chosen because it is both safe, and unlikely to cause high currents in input buffers due to the pins being in an indeterminate state.

Despite the "weak pull up" description, the pull-ups aren't that weak. 25K according to the cyclonge V datasheet. So if you need to overpower them you need a fairly strong pull down (I learnt this the hard way when using an IDT versaclock chip that had a combined clock output and configuration input pin to feed an altera FGPA).

* Apparently in older versions it was "as output driving ground", I don't know when this changed but IIRC it was a pretty long time ago.


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