Still learning, but this question is bugging me. I finally sort of understand how Flip-Flops work, and how that is used to maintain Shift Registers and such.

From the wiki page: "Each bit in an SRAM is stored on four transistors"

Why four? SRAM is a series of Latches (or flip-flops) correct?......flip-flops only have two Transistors correct? Unless im confused which i might be?

I've seen the schematic of a Flip-Flop of course (using NAND gates and such)? But NAND gates take more than one transistor to build yet i've seen sample Flip-Flops (Using LEDS) with just 2 Transistors?

As you can tell im a bit confused. SRAM is saying it needs 4 Transistors to store a bit......yet i've seen 2 Transistors store a state (which I guess could be considered a bit), and NAND gate flip flops (which surely take more than 1 transistors to make a NAND gate?

Im thinking of normal Bi-polar junction Transistors however, and upon further reading it appears "Most" SRAM uses FET's....would that have any difference however in how they are constructed?


You have to keep transistors and gates apart.

Four transistors is not bad to store a bit of data. If you would use a couple of gates you'd need at least 8. (A 2-input NAND gate consists of 4 transistors.) An SRAM cell is basically two inverters connected back to back, so that they one keeps the level of the other alive. One inverter consists of 2 transistors, so that's 4 in total.

enter image description here

Actually it's possible to use even less hardware to store a bit, and that's what DRAM does: it stores a bit as a voltage level in a capacitor. This means that you can get a lot more data in a square mm of DRAM than in an SRAM. Unfortunately the capacitor voltage leaks away, so the DRAM has to be refreshed continuously.

  • \$\begingroup\$ Actually the cell you showed is a 6-transistor, because you count also the word-line ones. The 4-transistors cell uses pull-up resistors. \$\endgroup\$ – clabacchio Apr 18 '12 at 15:27
  • \$\begingroup\$ Ok I think I understand....but then how come i've seen tutorials and such that are storing "bits" in the form of an LED with just 2 transistors? or is that not really the same thing? Or with 4 Transistors are able to store 2 bits?....if that makes any sense \$\endgroup\$ – user3073 Apr 18 '12 at 15:51
  • \$\begingroup\$ @clabacchio - Correct, but in ICs resistors are implemented as MOSFETs. But indeed there's a difference in the load's gate connection . \$\endgroup\$ – stevenvh Apr 18 '12 at 16:19
  • \$\begingroup\$ True, in fact I think that the resistor-transistor cell is not widely used in VLSI. \$\endgroup\$ – clabacchio Apr 18 '12 at 16:28

There are various ways of making a 1-bit memory cell. However, those implemented with active logic are all one way or another a amplifier with positive feedback. As you mentioned, this can be done with two transistors and some resistors:

Look at this carefully and you will see it has two stable states, either Q1 on or Q2 on. However, it also has a significant drawback, which is that it draws current continuously. The resistors can be made quite high, but there are still many many bits on a modern static RAM chip and the currents for each bit would add up.

The basic CMOS inverter doesn't draw current (except for small leakage) when solidly in either state. This is a simple two-FET circuit. A PFET can pull high and a NFET pull low. The gates are tied together and the thresholds set so that only one of the two FETs will be on when the gates are fully high or fully low. However, a inverter doesn't provide positive gain. That can be solved by using two inverters back to back. Two inverters in a row make positive gain. If the two inverters are connected in a loop, then they have two stable states. One will be high and the other low, but the circuit is stable in both the high-low and low-high states. Since a CMOS inverter is just two FETs as described above, this memory cell is 4 FETs with the big advantage that it doesn't take any current when not switching. As Steven said, four CMOS FETs per bit isn't really all that bad. Everything is a tradeoff.

  • \$\begingroup\$ I think I understand, but im a bit confused at what you mean that a CMOS inverter doesn't draw current? How can the Inverters keep their state without drawing current? or is it relying on the feedback from the other inverter to keep it's state (I guess what im asking is how can it "not draw" current and keep it's "state".....voltage would leak out of the system eventually right?) \$\endgroup\$ – user3073 Apr 18 '12 at 15:56
  • \$\begingroup\$ @Sauron: A CMOS inverter is just two transistors stacked between power and ground. Only one is on at a time, so not current flows thru them when not switching. However, the output voltage is still held because one of the transistors is on. It works because MOSFETS are controlled by voltage, not current, so no current is required to keep them on. \$\endgroup\$ – Olin Lathrop Apr 18 '12 at 18:17
  • 1
    \$\begingroup\$ @Sauron: Olin describes the usual thought process. However there is in reality an extremly small leakage current. Unless doing fancy things like deep submicron circuits, or using low threshold transistors, this leakage usually so small that you can count it as zero in most caluclations. However this does prevent SRAM from being usable as non-volatile storage. Nevertheless, as long as you keep supplying power, the current usuage is effectively zero. \$\endgroup\$ – Kevin Cathcart Apr 18 '12 at 19:43

CMOS AND gates require 4 transistors (the minimum) for the 2-input gate. enter image description here

You can go down to 2 in resistor-transistor logic:

enter image description here

For registers, there are many topologies but the simplest requires at least a ring with two inverters, thus 4 transistors plus the writing buffers, so about 8 transistors.

SRAM need 4 transistors in the smallest simplest design (resistor-transistor, but resistors are far bigger than transistors in MOS technology), 6 for a full MOS cell. You can have 1-transistor DRAM though, using a capacitor to store the value; but that's again dynamic logic, and it's the highest integration possible.


Circuits which use transistors, resistors, and capacitors, can get by with many fewer transistors than circuits which use transistors alone. Back in the days of discrete components, replacing a transistor with a resistor would save cost. Resistors, however, are horribly inefficient and, in integrated-circuit implementations, they actually cost substantially more than transistors. Many applications which would use them could substitute current sources, which weren't quite so bad in terms of cost, but horribly inefficient in terms of energy.

If one wishes to store a bit of information without significant ongoing power consumption, the most compact way to do that is to use two inverters, which will require an absolute minimum of four transistors to hold the data. Since holding information is generally only useful if one has a means of supplying it in the first place, an SRAM cell will add some additional logic to the four-transistor cell to allow access to it. To switch things "cleanly" without bus contention would require four additional transistors; in practice, it is generally possible to yield acceptable performance with two.


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