I'm trying to understand which logic is implemented by the following CMOS gate.

enter image description here

Comparing with the following CMOS NAND gate, I feel like the above logic gate could be a NOR gate, I'm not sure. My problem is that there are some extra details on the above CMOS gate which I'm not familiar with, like Via or Poly contact. Also I assume Metal 2 is the output, but I don't understand why Metal 2 (output) is directly connected to Metal 1 (drain/source) with Poly contact. I wonder if anybody can explain why.

enter image description here


You are right. It is a NOR gate. But the layout is extremely confusing.

Via typically refers to contact between metal layers. Here this is the contact between Metal2 and Metal1. By convention, metal are numbered starting by the lowest level first (closest to the transistors/substrate).

Poly contacts refer to contact to the contact between the lowest level metal [Metal1 here] and the polysilicium layer Poly that forms the gate of the transistors. Here I am confused by the layout because the poly contacts are not landing on any poly layer. Therefore, although the drawn poly contacts are connected to Metal1 they are not connecting to other layers because not on top of Poly. So we can consider them as disconnected.

The Metal2 trace is also confusing because it extends to an unused Poly contact. So it looks like it is making contacts on 4 points but in fact it is doing it only on 2 (the red square on my edited picture).

I edited your image adding the schematic of the transistors in blue and path between transistor in red. The active vias/contacts are circled in red.

Layout with schematic elements

So the resulting schematic of the circuit is the following:


simulate this circuit – Schematic created using CircuitLab

That is the schematic of a NOR gate.


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