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There is a big confusion in my head about debug connectors for ARM microprocessors. If I just take a look at this documentation there are a couple of JTAG connectors mentioned:

  • Cortex 10-pin JTAG/SWD (usualy 0.05" pitch) which supports JTAG debug, SW debug, SW viewer

enter image description here

  • Cortex 20-pin JTAG/SWD/ETM (usualy 0.05" pitch) supports JTAG debug, SW debug, SW viewer, trace operations.

enter image description here

  • Traditional 20-pin JTAG/SWD (usualy 0.10" pitch) supports JTAG debug, SW debug

enter image description here


Now I could only find schematic on how to connect the Traditional 20-pin JTAG/SWD to the microcontroller and it is this one:

enter image description here

To completely understand the schematic I will paste power section as well. This is important, because it looks like entire circuit is powered by JTAG pin 19 which is connected to power regulator and then goes back to the JTAG connector pins 1, 2, 13...

enter image description here

Does anyone have any schematics for the other two?

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    \$\begingroup\$ the minimal you need for a cortex-m and often the only ones you need are swdio and swdclk. And a ground and the debugger may wish to have a voltage reference to know say a 1.8 volt part from a 3.3v or other (know where to sample swdio and how high to drive swclk it may use your voltage ref possibly as vccio). the other signals are for a universal arm jtag header and debugger that covers more members of the family jtag and swd. \$\endgroup\$ – old_timer Apr 29 '17 at 12:32
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    \$\begingroup\$ Do you know if you are going to use JTAG or SWIO for debug? They are both debug/test ports, but some chips and IDEs offer different capabilities with them. The extra lines on the larger connectors (DBGRQ or Tracedata) provide extra, processor specific, debug access \$\endgroup\$ – pscheidler Mar 18 '18 at 15:24
  • \$\begingroup\$ I will use JTAG. \$\endgroup\$ – 71GA Mar 19 '18 at 19:04
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Here is the 10 pin one from my design using both SWD and JTAG

enter image description here

Couple of points:

  1. VCC line is just to tell ST Link or other programmer the IO levels of debug interface.
  2. KEY pin is optional. it has been taken care with connector type which do not allow wrong insertion It is not a signal, just a way to tell that there will be no pin on that position, so that we can also use low cost connector on board without pokayoke
  3. Terminations - My design is for STM MCU, but it applies to all ARM MCUs in general. enter image description here

One example for 20 pin. If trace pins are not sued, then they can be left open

enter image description here

because it looks like entire circuit is powered by JTAG pin 19 which is connected to power regulator and then goes back to the JTAG connector pins 1, 2, 13...

DBGACK Pin - ”Debug Acknowledge” (high active) is an input of the debugger to sense the processors halt status. This is used in multi processor system and the pin itself may not be available on all MCUs.

Hence, please check JTACVCC source. JTAG connector is not supplying that for sure.

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