1
\$\begingroup\$

I have one 8 bit flash interface on a MCU. I multiple flash ICs. Each flash IC has one 8 bit parallel interface.

One option is to use a multiplexer. The other option to tie all of the parallel interfaces together and turn only one flash IC on at a time. Turn off as in leave VDD floating.

What should I use?

\$\endgroup\$
6
  • 1
    \$\begingroup\$ Do they not have any sort of enable or chip select input? \$\endgroup\$
    – Hearth
    Commented Apr 29, 2017 at 23:54
  • \$\begingroup\$ @Felthry I also want to reduce power consumption by turning the unused flash off. Will the input buffer die if I force power through it while turned off? \$\endgroup\$ Commented Apr 29, 2017 at 23:58
  • \$\begingroup\$ What's the part number on your flash memory? \$\endgroup\$
    – Hearth
    Commented Apr 30, 2017 at 0:18
  • \$\begingroup\$ @Felthry digikey.com/product-detail/en/micron-technology-inc/…. I need 4 of these for redundancy. \$\endgroup\$ Commented Apr 30, 2017 at 0:49
  • \$\begingroup\$ I can't find anything about an input buffer in the datasheet for those. Their standby current is only 10μA typical or 50μA max, anyway--and even at 3.3V that's a maximum of 165μW, or even 90μW if you use the 1.8V model. And that's the maximum! The typical standby power would be much lower (though you never can really trust the typical values on the datasheet--the particular one you happened to get, it seems, is always worse!) \$\endgroup\$
    – Hearth
    Commented Apr 30, 2017 at 1:06

1 Answer 1

1
\$\begingroup\$

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power con- sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn- chronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring.

m69a_2gb_nand.pdf – Rev. H 09/10 EN, page 18

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.