In todays personal computers and notebooks, what is usually used as a Voltage-Controlled Oscillator for generating clock signal for processor?

  1. Is that a crystal rather than RC circuit?
  2. Is it tuned by varicap?
  3. Does it contain reference voltage and comparator?
  4. What is a diagram/scheme of that circuit?
  5. Is frequency of the internal crystal the maximum possible output frequency?
  6. Does VCO work on clock signal or continuously?
  7. What is the physical principle behind changing the frequency? Can I see graphs explaining how it works?

EDIT Let me state, that I have read all the related Wikipedia pages, so please don't send me search through it again. That's pointless. I wouldn't have so many questions, if I haven't read about PLL's for hours and hours. Now I need to put all the information into frame. I'm asking for guidance. I understand it takes a person with very deep knowledge about the subject. So please if you don't have the knowledge, don't spam here. I am really interested in the subject. Thank you.

  • 2
    \$\begingroup\$ That's rather a lot of questions for one question; start with ti.com.cn/cn/lit/ml/snap001/snap001.pdf - it's NOT a crystal; it may incorporate a varicap diode. Maximum output is a design parameter - as fast as the VCO can go. \$\endgroup\$
    – pjc50
    Apr 30 '17 at 10:58
  • 2
    \$\begingroup\$ read "Wikipedia phase lock loop"; what is the physical principle behind changing the frequency? as with a pendulum, with two mechanisms for storing energy, some PLLs use LC oscillators with two clearly different energy storage mechanisms, and one is altered. The Quality Factor (often Zl/Rloss) contributes to total integrated time wavering of zero crossings. Other PLLs use a current to charge a capacitor; with only one energy storage mechanism and no resonance, there are 3 ways to vary the period. \$\endgroup\$ Apr 30 '17 at 13:11
  • \$\begingroup\$ @analogsystemsrf trust me, I read all the related wikipedia pages, but still have lots of unanswered questions. \$\endgroup\$
    – user50222
    Apr 30 '17 at 13:36
  • \$\begingroup\$ @pjc50 it's really just one question and the list is added just so people understand how deep I want the answer to go. \$\endgroup\$
    – user50222
    Apr 30 '17 at 13:37
  • \$\begingroup\$ there is no one answer, so you need to ask a one answer question. second there are answers on wikipedia, go investigate them. you want to see how this works take spice or some other simulator and use the information on wikipedia... \$\endgroup\$
    – old_timer
    Apr 30 '17 at 14:09

The question is ill-formulated. Is this about a clock FOR the processor, or about MAXIMUM INTERNAL CLOCK in the processor? The tag "overclocking" seems to hint for the latter.

So, the clock FOR a processor is usually coming from a crystal-stabilized oscillator, from an external one, or from built-in.

The INTERNAL clock inside a processor is generated from a special unit called PLL - Phase Locked Loop, which includes a VCO (Voltage-controlled oscillator) as inseparable part. The idea behing PLL is well introduced in this Wikipedia article.

The design of VCO can vary, and I believe in most current processors it is based on idea of ring oscillator having variable voltage-controlled delay. Several ideas of modern VCO designs are illustrated in this lecture.

The VCOs in microprocessors usually run continuously at a pretty high frequency - several GHz. Then digital dividers (in reference and VCO channels) mix at a phase detector, which outputs analog voltage that controls the VCO, and the properly filtered feedback locks the frequency to one from a working set of internal frequencies. These frequencies are used in various technologies to align the execution speed of a microprocessor with manageable power consumption, dynamically.

To achieve the goal of several internal frequencies, the VCO must operate in certain linear range of frequencies, to get into the frequency lock defined by digital frequency dividers, so no, it doesn't operate at its maximum, but rather somewhere in between min and max.

Be aware that the frequency synthesis is one of the most challenging areas of electrical engineering, so you should note that the lecture level is 620, post-graduate level, far from 101.


Is that [VCO] a crystal rather than RC circuit?

VCOs don't use crystals†, but VCOs don't necessarily use a RC circuit for timing either. Voltage controlled oscillators are a broad class of different designs.
Crystal oscillators are frequently used to generate the reference frequency for a phase locked loop (PLL), but phase locked loops are not VCOs. VCOs are a building block of PLLs.

†Crystal oscillators whose frequency can be very slightly tuned (only a tiny fraction of a percent) with a control voltage do exist, but they are probably not what you meant.

Is it [VCO] tuned by varicap?

That's like asking "are trucks powered by diesel". Many (especially harmonic oscillator-based) VCOs are, many (especially relaxation oscillator -based) aren't.

Does it [VCO] contain reference voltage and comparator?

Relaxation oscillator -based designs usually do in some form or another, but other VCOs use a different mechanism.

Is frequency of the internal crystal the maximum possible output frequency?

VCOs don't generally have crystals, they are just oscillators whose oscillator frequency is roughly but monotonically proportional to the control voltage. You might be thinking of phase locked loops (PLL), which often (but not always) use a crystal oscillator as a reference oscillator. A PLL is a circuit which produces an integer multiple of a reference frequency by automatically tuning a VCO to keep it in sync with the reference.
The output of a PLL is not limited to the reference frequency (which is often generated by a crystal oscillator), it can go many times higher than that. That's a big part of the appeal of PLLs.

Does VCO work on clock signal or continuously?

Continously. They may output a clock signal, they don't need one themselves.

What is the physical principle behind changing the frequency? Can I see graphs explaining how it works?

You increase the control voltage, the frequency increases. I don't understand why you'd want a graph to understand that. The physical principle varies, but in general there are two types:

  • Harmonic oscillators use a wideband amplifier feeding back into itself. A specific frequency can be generated by adding a band-pass filter into the feedback path, so that only oscillations at a single, desired frequency can sustain themselves. To change the output frequency, the filter is modified so that the passband is changed, achievable with e.g. a varicap.

  • Relaxation oscillators repeatedly charge and discharge an energy storage element like a capacitor or inductor, with the charge and discharge time determining the output frequency. The frequency can be varied either by changing the capacitor/inductor charge rate, or the thresholds at which the circuit switches from charging to discharging and vice versa. This type is what you usually find as part of the clock generation circuitry of digital electronics like microprocessors.


Think about the problem that is being solved for a second. You want the inside of the chip to run at some frequency, you want to be able to choose different frequencies for various reasons (or pick a specific one for one or more reasons). You take a crystal (accurate) based oscillator and you want to multiply that essentially.

Think of the things your professors said not to do, dont do this or the circuit will oscillate. The term metastability might have come up in the lecture as well. In this case you actually want that, a semi-controllable unstable oscillator that you can loosely control.

So you need to have a loosely controlled oscillator, something you can build in silicon, wrap that with a control system (PLL) and there you go. Say I want to turn 4Mhz into 16, so lets say I want my VCO then to be 16x that. I take the output of the vco put it into a counter, I sample/reset the counter every tick of the 4MHz clock, if it is less than 16 counts then I adjust the VCO to go faster, when it gets to 16, great, so I keep that control setting, if it drifts to 17 I slow it a little, drops to 15 I speed it a little...a control system...I design the oscillator and its control such that it cant go out of control to fast, dont want one 4Mhz cycle to be 16 counts then the next 47 then the next 3. Thus the time it takes to settle a PLL based clock in a processor/chip before you can use it (usually documented in the datasheet). Then I can use another (digital) counter to divide that 16x down by for so I went 4*16/4 = 16mhz.

Doesnt have to be a digital counter, just one possible way to do it, it can be some sort of analog solution (thus the term PLL, phase locked, using the phase difference), but at the end of the day it needs to track N times the reference clock which was the whole point. The delta used in the control system doesnt have to be a whole count off, that would possibly be pretty bad, you could have a digital count that is a coarse grained control loop and then for the fine control loop you use an analog comparison of the reference clock state change and the Nth VCO state change.

Your PLL output is not going to be as good as the reference clock, it is going to have jitter to it, that is expected it uses a control system, so this is implied.

You may or may not be old enough to know what 7400 logic is. But you could take an inverter and feed it back or take an odd number of them and see what happens. It makes no sense on paper if the output is a 1 then input is a 1 then the output is a 0 then the input is a 0, assuming an instantaneous state change. Electricity is bound by the "speed of light" through a material...it has a speed limit...that limit creates a delay, so if you can kick the circuit off into oscillation it will hopefully continue to oscillate. Search for ring oscillator on wikipedia.

A quote from wikipedia

"The voltage-controlled oscillator in most phase-locked loops is built from a ring oscillator"

You can certainly make a NOT gate in silicon on a chip, what other circuits can you make, and what in those circuits can you control in silicon. You cannot make a resistor with a wiper, you are not going to wrap wires around a core and make an inductor (although as with a pcb you can horizontally wiggle a trace back and forth), but you cannot vary that trace once it is placed on the chip, nor make the plates of a capacitor move, nor move a wiper along a metal to make a mechanical variable resistor. Sure you can absolutely make and use a varicap. As pointed out at wikipedia they are commonly used in VCOs.

Vericap on wikipedia also leads into frequency multiplication, where you create a harmonic the filter it out. But would that then need a phase locked loop?

Can you make a circuit, you can build on a chip, that is a voltage controlled oscillator, wrap a PLL around it to somewhat control it to either exactly multiply the reference clock by N or to multiply it by X then divide by Y to get the desired result (not uncommon for the VCO frequency to be in a range higher than the PLL output frequency to be divided to the desired frequency). Yes, obviously it has been done countless times. Problem is there is more than one solution, we cant give you a single answer here if that is what you are after, if there are 100 solutions and someone posts one, they are 99% wrong...

You want to know how they do it in a computer processor? Depends on the processor, the foundry, the process used, the IP used, and which pll in that processor, there may be several, and they might have used a different one for each, depends on the application (core cpu, ethernet/network, pcie, video, etc), the answer can vary at the same foundry with the same chip company but with a different process, each process may dictate or grant the opportunity for a different solution, or not...look at sandy bridge and ivy bridge, not sure exactly how much of it was the same it is intel after all, but it was declared a die shrink from 32nm to 22nm, how much IP was the same from one process to the other, the high level microcoded archtecture, sure just verilog re-compile, but the specific gates, and IP like the I/O pads and PLLs and such, were those complete replacements? Possible.

So IMO your question is not a fit for this site, it does not have one answer, it cannot be summed up in detail with a single circuit, so are you after the concept of how it works, that is sorta okay as a question as that sorta has an answer, see wikipedia or see above. Or are you specifically wanting the circuit for a specific chip from a specific foundry with a specific process using specific IP? Your question is too broad...If you change it to ask a question with one answer, then perhaps someone here can give a single accurate answer.

Spending only a handful/dozen hours reading is not enough to understand the concept with some example circuit details, it can take years in college to get the foundation required, that is more than a couple dozen hours of reading wikipedia. The answers are already there, but the understanding of what is being said might take years of study. Is that the problem here, is that your question?

You said you read all the related articles so: you saw the vericap comment you saw the ring buffer and that comment about VCOs, you read up on PLLs and control systems in general, you examined what a NOT gate was with example circuits. So what specifically do you not understand, what specifically is your question? Something that has an answer.


There are a huge number of ways and many crystals and many clocks in every PC for different purposes. RTC, GPU, FSB RAM, Core, I/O etc.

With each vendor (AMD, Intel, Qualcomm, etc) different approaches are used but clocks are digitally programmable by BIOS , OS and CPU itself especially in mobile CPU's and those with Thermal Clock Management.

Both Vdd for core and memory can be tuned with FSB ratios to reduce the step up ratio the core clock by changing the step down ratios with both integers for real-time control and fractional N PLL's for precision f control.

The crystals are similar stability to a typical watch but using AT-cut crystals not MEMs tuning fork resonators found in watches and thus operate at higher f.

Intel's , AMD's and other's designs are proprietary.

This PLL description is an example of how it is done inside a Freescale DSP.




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