In this datasheet the logic diagram shows three cascaded inverters to get a simple inverting function.
So that would mean that you have three PMOS-NMOS pairs in succession. Why is this better than just the two MOSFET inverter?
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It's for obtaining the right driving strength, the right input capacitance and the lowest latency.
Logically there is no difference between one or three inverters, but...
This kind of buffer is made to drive a higher load than just a single inverter, and this has to do with speed. The problem is that a CMOS gate can drive a current proportional to the width of its channel: doubling the channel width, you'll be able to charge a given capacitor twice as fast.
So, why not just use very wide transistors to have the highest current?
Because, if you double the channel width, you also double the input capacitance of the gate, so the stage before will take twice the time to drive the gate. So you need a gate which has the minimum possible input capacitance, while having as much as driving strength as possible.
This is obtained by cascading several inverters (the most elementary CMOS gate) with increasing channel width, so that the first has the required input capacitance and the last has the required driving strength.
The tradeoff now is that each inverter has also a fixed amount of latency, so you can't solve it just cascading many many inverters. There are specific formulas, also described in Rabaey-Chandrakasan-Nikolic book about integrated circuits design (expensive but very good!).
A CMOS inverter can be as little as an N-Channel + P-Channel pair - as shown diagrammatically in this A series CMOS CD4069 hex inverter
B series and other later CMOS were buffered or had additional 'stuff' in the signal path. And even the A series diagram is representational and does not shown exactly what 'happens inside'. So we can have more than just two MOSFT transistors even in a single inverter. Your example is one such.
The usual reason to increase complexity from a simple transistor pair is "buffering". The output pair will have high current drive capability. The inpu pair can be optimised for gain or low or high gate threshold voltage etc. One you have one extra inverter you need another to maintain net inversion.
In external circuits extra series inverters may be added to give extra propagation delay - not a requirement here.