In this datasheet the logic diagram shows three cascaded inverters to get a simple inverting function.

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So that would mean that you have three PMOS-NMOS pairs in succession. Why is this better than just the two MOSFET inverter?



It's for obtaining the right driving strength, the right input capacitance and the lowest latency.


Logically there is no difference between one or three inverters, but...

This kind of buffer is made to drive a higher load than just a single inverter, and this has to do with speed. The problem is that a CMOS gate can drive a current proportional to the width of its channel: doubling the channel width, you'll be able to charge a given capacitor twice as fast.

So, why not just use very wide transistors to have the highest current?

Because, if you double the channel width, you also double the input capacitance of the gate, so the stage before will take twice the time to drive the gate. So you need a gate which has the minimum possible input capacitance, while having as much as driving strength as possible.

This is obtained by cascading several inverters (the most elementary CMOS gate) with increasing channel width, so that the first has the required input capacitance and the last has the required driving strength.

The tradeoff now is that each inverter has also a fixed amount of latency, so you can't solve it just cascading many many inverters. There are specific formulas, also described in Rabaey-Chandrakasan-Nikolic book about integrated circuits design (expensive but very good!).

  • \$\begingroup\$ Thanks (I don't think I'll buy the book at this time :)) \$\endgroup\$ – Federico Russo Apr 19 '12 at 10:28
  • \$\begingroup\$ I would conjecture (you can tell me if I'm correct) that the reason for using more than one instead of exactly one is to allow a fast output stage without a large input capacitance; the reason for having three rather than two isn't to allow a progression of sizes (though if three are needed, one may as well size them progressively), but rather to yield an inverted output (since using just two would leave one with a non-inverted output). \$\endgroup\$ – supercat Apr 19 '12 at 19:12
  • \$\begingroup\$ @supercat In Rabaey's book it's explained quite extensively, but it appears that in many cases 3 is good for an inverting buffer and 4 is good for a non inverting...so yes, 3 is an odd number, but eventually is better than 5 :) \$\endgroup\$ – clabacchio Apr 19 '12 at 21:36

That is called a super buffer. It provides a high current capability at the output, keeps a low input capacitance, and tries to minimize the total delay, by progressively sizing the inverters (larger towards the output).

References: A, B, C, D.

  • \$\begingroup\$ Never heard that name...And it's not always true that the delay is increased, depending on the load \$\endgroup\$ – clabacchio Apr 19 '12 at 10:50
  • \$\begingroup\$ @clabacchio You are right. I edited it. \$\endgroup\$ – Telaclavo Apr 19 '12 at 10:52
  • \$\begingroup\$ Why can't a single gate do that? What's different between the first and the last gate? \$\endgroup\$ – Federico Russo Apr 19 '12 at 11:46
  • \$\begingroup\$ @FedericoRusso A single gate can't do that, because if it were to provide high current capability at its output, it would also exhibit high input capacitance. The difference between the first and the last gate is their sizes. They grow from input to output. \$\endgroup\$ – Telaclavo Apr 19 '12 at 11:53
  • \$\begingroup\$ @FedericoRusso isn't that explained enough in my answer? Not to get more attention, but I thought to be exhaustive.. \$\endgroup\$ – clabacchio Apr 19 '12 at 12:09

A CMOS inverter can be as little as an N-Channel + P-Channel pair - as shown diagrammatically in this A series CMOS CD4069 hex inverter

B series and other later CMOS were buffered or had additional 'stuff' in the signal path. And even the A series diagram is representational and does not shown exactly what 'happens inside'. So we can have more than just two MOSFT transistors even in a single inverter. Your example is one such.

The usual reason to increase complexity from a simple transistor pair is "buffering". The output pair will have high current drive capability. The inpu pair can be optimised for gain or low or high gate threshold voltage etc. One you have one extra inverter you need another to maintain net inversion.

In external circuits extra series inverters may be added to give extra propagation delay - not a requirement here.

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    \$\begingroup\$ I think there's nothing wrong with saying NMOS for an N-channel MOSFET. \$\endgroup\$ – stevenvh Apr 19 '12 at 7:56
  • \$\begingroup\$ I don't doubt it. Tens and tens of books use "NMOS". Example: fabweb.ece.illinois.edu/recipe/pr1.aspx \$\endgroup\$ – Telaclavo Apr 19 '12 at 10:41
  • \$\begingroup\$ That link is to an Unbuffered B series 4069. Some B series devices, eg 4011, 4069 are available in both buffered and unbuffered variants. \$\endgroup\$ – MikeJ-UK Apr 19 '12 at 15:14

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