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Here is my gate level description of an S-R latch:

module SR_Latch_Nand(input S, R, C, output Q, QB);
wire s1, r1;
nand #8 n1(r1, R, C);
nand #8 n2(s1, S, C);
nand #8 n3(QB, R, Q);
nand #8 n4(Q, S, QB);
endmodule

and here is test bench for this S-R latch:

module SR_Latch_Nand_TB();
logic s, r, clk;
wire q, qb;
SR_Latch_Nand sr(s, r, clk, q, qb);
initial begin
  s = 0; r = 0; clk = 0;
  #100 s = 1;
  #100 clk = 1;
  #100 clk = 0;
  #100 clk = 1;
  #100 s = 0;
  #100;
end
endmodule  

When i check waverform, value of Q is x at most of the times. other times it's mostly incorrect. I've tried to preset values of q, qb but it still doesn't seems to work.

So can you tell what's the problem with this code?

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0
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The problem is with your testbench and the way you set r and s. If they are both active low, then make sure your testbench tests only one active low.

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0
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The code of SR_Latch_Nand is wrong. You missed to use the s1 and r1 for the output flops. Corrected SR latch module should be.

module SR_Latch_Nand(input S, R, C, output Q, QB);
  wire s1, r1;
  nand #8 n1(r1, R, C);
  nand #8 n2(s1, S, C);
  nand #8 n3(QB, s1, Q);
  nand #8 n4(Q, r1, QB);
endmodule
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