0
\$\begingroup\$

I have this circuit below which has kp=200u,Vto=0.6,L=1u,W=10u,nmos transistor

Can anyone explain me how VS(voltage in source) becomes negative?Also I know that, in this cuircuit the the maximum voltage should be VDD and the minimum 0V.How this negative voltage appears.And one more question.I expected that this current (which produced by ideal current source) couldn't flow in the circuit because VGSenter image description here

\$\endgroup\$
  • \$\begingroup\$ LOL you have a ideal current source in the source terminal and this is why you have a negative voltage at source. \$\endgroup\$ – G36 May 3 '17 at 8:47
  • \$\begingroup\$ Thanks G36. But this cirucit can appear a negative voltage if ground is the minimum voltage? \$\endgroup\$ – elecV1 May 3 '17 at 8:51
  • 1
    \$\begingroup\$ Yes it can. The ideal current source can do this. \$\endgroup\$ – G36 May 3 '17 at 8:53
  • 1
    \$\begingroup\$ In addition in LTspice you can tell the sim that you are using a ideal current source as a load. So this will not happen. \$\endgroup\$ – G36 May 3 '17 at 9:10
1
\$\begingroup\$

The ideal current source will reduce the voltage at the source (taking it as far negative as necessary) to turn the MOSFET on (gate-source voltage) in order to draw 100 uA. It will do what it has to because it is an ideal source and doesn't care about power rails.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.