5
\$\begingroup\$

Can anyone explain why some engineers use multiple parallel identical capacitors on MCU power inputs, memory power inputs... Sometimes there is up to 6, 7 or even 8! Here is one example I found for LPC4088. enter image description here

This is confusing to me because I usually use one big electrolytic capacitor (to deal with low frequency ripple) and one small ceramic capacitor (to deal with high frequency noise) in parallel... Just like it is described here.

Does it have anything to do with input impedance of VDD/VDDR pins in the image? VDD is 3.3V and is supplied through a regulator LM117-3V3 like this: enter image description here

I can't seem to find the info about input impedance for VDD and VDDR pins anywhere in LPC4088 datasheet.

\$\endgroup\$
19
\$\begingroup\$

You normally want a decoupling capacitor (usually ceramic) physically near to each power pin in order minimize the effects of parasitic inductance. This is why multiple capacitors are used.

Since the schematic isn't normally intended to reflect the physical layout, these capacitors are simply grouped together in a convenient place. Notes from the design engineer to the layout engineer (especially if they are different people) explain what is needed in terms of the physical layout. These notes can appear in the schematic itself, or in a separate design rules document.


There are other reasons to use multiple capacitors, too. These tend to come up more with respect to the larger capacitors (e.g., electrolytic) used in power-handling circuits, such as switching power supplies.

  • Sometimes a single capacitor won't fit in the space available, while multiple smaller capacitors will.

  • Sometimes a single capacitor won't be able to handle the AC (ripple) current, while multiple smaller capacitors will.

\$\endgroup\$
  • 5
    \$\begingroup\$ One could argue the schematic should reflect such crucial things. Mine do, always. \$\endgroup\$ – Janka May 3 '17 at 16:24
  • 1
    \$\begingroup\$ @71GA: Yes, if multiple power pins are adjacent, they can be served by a single external capacitor. \$\endgroup\$ – Dave Tweed May 3 '17 at 16:29
  • 1
    \$\begingroup\$ Sometimes one cap per pair of power pins is used, even if the pins aren't right next to each other. This can simplify the layout and consume less area while still providing reasonable decoupling. \$\endgroup\$ – alex.forencich May 3 '17 at 18:22
  • 1
    \$\begingroup\$ With that package where you can't actually get to the pins, I'm actually surprised there are not eight caps spread round it, esp since a lot of them are in the inside square. \$\endgroup\$ – Trevor_G May 3 '17 at 18:47
  • 4
    \$\begingroup\$ Reason #3: You can sometimes get a cheaper BOM with fewer part numbers if you parallel a few caps with common values you're already using. \$\endgroup\$ – Nick T May 3 '17 at 22:30
6
\$\begingroup\$

EDIT: Er, oops, I managed to miss that this was specifically about decoupling capacitors. The below is still a few general reasons one might want to put multiple capacitors in parallel, though, so I will leave it unless others think it should be removed.

There are a number of reasons this can be beneficial.

First, and perhaps most obvious, is that it's sometimes cheaper to get ten small capacitors than it is to get one with ten times the capacitance. Especially if you need a very large capacitance, this can be a good option.

A less obvious but still important one is that putting capacitors in parallel results in a lower equivalent series resistance than a single capacitor of larger value. ESR is a major problem in situations like switching power supplies, as it's a major component of the energy loss.

And one more reason I can think of is that, if they're experiencing very high currents, multiple capacitors would not only reduce the ESR and thus reduce the heat generated, it would also spread the heat out between different capacitors, and the larger surface area allows for more effective cooling. So there's less heat and it's easier to get rid of.

\$\endgroup\$
  • \$\begingroup\$ +1 cheaper BOM can be a reason. I'd just re-edit/rephrase your answer so the "EDIT" is just part of the prose :P \$\endgroup\$ – Nick T May 3 '17 at 22:31
  • \$\begingroup\$ Not sure how to rephrase it to make that work... though I could just be a bit too tired! \$\endgroup\$ – Hearth May 4 '17 at 2:15
4
\$\begingroup\$

As others have mentioned, it's likely they were only drawn that way because the designer decided they should have many caps due to the number of pins. They probably drew them as a group rather than assigning them because, looking at the power distribution on the device below, it would be rather hard to decide where to put them.

It's actually one of those cases where having some on the rear of the board makes a lot of sense.

enter image description here

Actually I am surprised there are only six of them.

\$\endgroup\$
3
\$\begingroup\$

All Caps have an equivalent circuit based on chemistry, construction and geometry with a minimum of ESR,C,Rleak, ESL components shown below. Some have even more complex equiv ccts. which is why cap substitution must consider the application, schematic, design notes and layout to ensure no glitches in choices.

This is the reality of electronics when high speed rise times switching dumping CMOS switch capacitance must be suppressed to improve signal margins by proper decoupling of supply and ground.

This is also why some people use ECL and CML due to lack of current spikes from current mode differential logic when operating at extreme logic speeds and need high noise immunity.

MLCC's are typically 2x1 LxW like 1206, 603 402 and thus have a certain inductance based on this size. But generally have very low time constant compared with electrolytics when you use the ESR*C=T value which means the upper frequency near 1/T can be much higher for ESR decoupling.

  • special low ESL MLCC's use LxW=1x2 just the opposite to reduce the inductance and thus raise the SRF, \$f=\frac{1}{2\pi\sqrt{LC}}\$ made by companies such as Murata and TDK.

Now when you put many 2x1 caps in parallel such that the LxW becomes n wide you accomplish the same thing by reducing to L/n and thus raising SRF by \$\sqrt n\$ while reducing the ESR by n such that the result is much better than a big MLCC of the same uF value. Too low an ESR can also raise Q of SRF peaks, when multiple ultra low ESR C's are used so read Murata TDK details on this if you don't understand yet.

This is significant, when you have to suppress current spikes from CMOS logic with >=1ns rise times that have an output Coss capacitance and 25 to 50 Ω RdsOn for 74ALVCxx or ARM uC's or to 50 Ω for 74ALCxx CMOS. Coss rises with reduced RdsOn in MOSFETs but also reduces with lithographic size. If you imagine a capacitance divider with a Vss switched voltage, not only is the ESR/RdsOn ratio important but the net Coss/C(f) for decoupling over many decades of f .

The other factor is distributed Caps so that track inductance does not cause a lower SRF than required and closer location of decoupling cap to source reduces Vdd AND Vss spike noise. The result is often ripple not just due to poor scope probe methods but spike transfer function with resonant frequencies and C ratio reduction and ESR ratio reduction. (Both are voltage dividers when f < SRF))

schematic

simulate this circuit – Schematic created using CircuitLab

The rise time varies with CMOS family and the current spikes depend on the number of synchronous switches inside the IC or group of IC's

\$\endgroup\$
0
\$\begingroup\$

Because they have to be close to the particular VSS pin, filtering the current for this one. This is only the way we draw them on the schematics, but of course it does not make any sense to place them together somewhere far from the micro. So the rule is: the capacitor as close as possible to the Vss pin

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.