With all due respect, you have missed the point of synchronous counters, and synchronous logic in general. This shows up in your use of the upper counter's RCO to drive the clock of the lower. Of course, using the 191 for the purpose you want is going to be a challenge anyways, due to the asynchronous reset.
In fact, there is no reason to think that your circuit works as you intend. When the upper counter hits zero, it will instantaneously load to 9 and force a count on the lower counter. So you will count 29,28,27,26,25,24,23,22,21,(20),19,18, etc, with the count in parentheses just a flicker. Not only that, but the RCO output will be prone to spurious runt pulses at clock edges, as internal propagation skew causes improper decoding of the outputs.
In general, making a power-on reset circuit is perhaps a bit (only a bit) more complicated than has been suggested. This is because you need a Schmitt trigger on the RC network - a large time constant will produce a slow transition through the logic threshold and there then exists the possibility of a noisy power-on signal, and that can have unexpected effects.
Finally, I would not recommend using a binary counter for decade work, or at least not one with an asynchronous load function. You are best off using a fully synchronous counter such as the 74LS169.
So, I'd recommend the following changes to your circuit, assuming you must use the 191
simulate this circuit – Schematic created using CircuitLab
In this circuit, all inverters are Schmitt triggers such as the 74LS14. You'll notice that TCO of the first stage connects to CTEN of the 2nd, and there is a common clock. Also, each TCO goes to a flip-flop which will generate a brief (100 usec or so) load pulse, which gets combined with the power-on reset generated by the RCD circuit on the left.
This is a really klugey circuit, and can be greatly simplified by using 74169s, as follows
simulate this circuit
You'll note how much simpler this is. However, you do need to be careful of one thing. Since the load function is synchronous, the power-on reset must be long enough to guarantee that at least one clock edge occurs while the reset is active (low). If you don't do that, the reset will not work reliably.