I am reading USB 2.0 standard, particularly about High-speed part, and I can't understand why do we consider that HIgh-speed USB uses differential signaling. Or at least why it is balanced? For transmitting logic 0 or 1, USB transmitter drives either one line or another with 17.7mA, and if said differential, I would expect currents with the same intensity but opposite directions. Because of my previous problems to understand this issue, i am not able to understand what is than a common mode on the USB bus in High-speed mode.
USB signaling is called differential because it is differential. The state of bus is either one line (D+) is HIGH, the other (D-) is LOW. And vice versa. The receiver is connected in a differential way, and senses either positive DIFFERENCE, or negative. So it is differential.
The idea that current should be either sourced or sunk is fairly narrow. For example, the very popular LVDS signaling uses two levels on each of signal pair of wires, VH is 1.4 V, and VL is 1.0 V. Yet no one is questioning differentiality of this signaling standard.
Same in USB: for FS signaling mode, VH is 3.3 V, VL is 0 V on each individual wire. An the packets use alternative states (called J and K) to transmit information. The receiver senses either +3.3 V, or -3.3 V.
For the HS signaling the VH is 400 mV, VL is 0 mV, so the differential signal goes from +400 mV to -400 mV.
CORRECTION: In both cases the common-mode signal is half of nominal voltage swing. Section 126.96.36.199 of USB 2.0 Specifications explicitly mentions that nominal common-mode voltage for HS signaling is 200 mV.
When BOTH USB wires have additional offset, for example, due to signal shift in ground return wire (due to power supply current, which happens on bus-powered devices on long and/or skinny cables), the receiver must tolerate this within USB specified limits.
Common Mode voltage refers to both the AC and DC mean voltage "common to both" conductors.
The DC mean voltage is obvious when you see the levels, but of greater significance is the use of CML or current mode logic at high speeds where instead of using a voltage source with an RdsOn of 25 Ohms or so, it uses a current source switched between outputs that creates a voltage in the terminators on the bus, so that it is matched to the cable impedance and gives the best immunity from RF noise and lowest emissions of the RF signals.
CML is an offshoot improvement in CMOS from the bipolar days of ECL where differential current lines were used for > 1GHz speeds.
CML is not specifically mentioned in the spec, and there may some specific differences, but conceptually it is identical.
Learning the significance of CMRR on cables and differential impedance as well CM impedance differences are key to understanding how high error rates are achieved with wide eye-patterns from cable non-linearities. (kinks etc) and why 3m is the max length for USB3.
...but that's an inference to a deeper question.