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I am reading USB 2.0 standard, particularly about High-speed part, and I can't understand why do we consider that HIgh-speed USB uses differential signaling. Or at least why it is balanced? For transmitting logic 0 or 1, USB transmitter drives either one line or another with 17.7mA, and if said differential, I would expect currents with the same intensity but opposite directions. Because of my previous problems to understand this issue, i am not able to understand what is than a common mode on the USB bus in High-speed mode.

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    \$\begingroup\$ It's implicit that when one line is driving 17.7ma the other line will be sinking 17.7ma. The common mode voltage is the voltage present on EACH of the wires i.e. if one wire was at 3.7v and one at 2.5v you have a common mode voltage of 2.5v and a differential voltage of 1.2v. \$\endgroup\$ – Michael Shaw May 4 '17 at 13:39
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    \$\begingroup\$ I wouldn't say so. The standard says: "In order to transmit in high-speed mode, a transceiver activates an internal current source which is derived from its positive supply voltage and directs this current into one of the two data lines via a high speed current steering switch." Also, when you look in the eye diagram of the USB, the signal goes +-400mv, and in the case that opposite currents flow in both D+ and D- lines, it would produce differential voltage of +-800mV. \$\endgroup\$ – Nexy_sm May 4 '17 at 14:07
  • \$\begingroup\$ Can you point me in the direction of the document you are reading this from? * Found it, main spec document for usb 2.0 \$\endgroup\$ – Michael Shaw May 4 '17 at 14:57
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    \$\begingroup\$ @MichaelShaw in your example we'd normally say the common mode voltage is 3.2 V. \$\endgroup\$ – The Photon May 4 '17 at 15:02
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USB signaling is called differential because it is differential. The state of bus is either one line (D+) is HIGH, the other (D-) is LOW. And vice versa. The receiver is connected in a differential way, and senses either positive DIFFERENCE, or negative. So it is differential.

The idea that current should be either sourced or sunk is fairly narrow. For example, the very popular LVDS signaling uses two levels on each of signal pair of wires, VH is 1.4 V, and VL is 1.0 V. Yet no one is questioning differentiality of this signaling standard.

Same in USB: for FS signaling mode, VH is 3.3 V, VL is 0 V on each individual wire. An the packets use alternative states (called J and K) to transmit information. The receiver senses either +3.3 V, or -3.3 V.

For the HS signaling the VH is 400 mV, VL is 0 mV, so the differential signal goes from +400 mV to -400 mV.

CORRECTION: In both cases the common-mode signal is half of nominal voltage swing. Section 7.1.4.2 of USB 2.0 Specifications explicitly mentions that nominal common-mode voltage for HS signaling is 200 mV.

When BOTH USB wires have additional offset, for example, due to signal shift in ground return wire (due to power supply current, which happens on bus-powered devices on long and/or skinny cables), the receiver must tolerate this within USB specified limits.

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    \$\begingroup\$ The common-mode is not zero, but the mean of the voltages. \$\endgroup\$ – Chris Stratton May 5 '17 at 2:23
  • \$\begingroup\$ Well, it might be that I didn't understand differential signaling while at university, but I am pretty sure that in order to say some signaling scheme is differential it should have balanced currents in the lines, so that almost no current flows to the ground. Why I think USB is not differential signaling is because when sending 1, current flows from the current source through 45 ohm resistors at both ends of the transmission linea dn goes to the ground. The other line is passive, which means during one bit period, we do not have opposite sign currents which flows through both D+ and D- lines \$\endgroup\$ – Nexy_sm May 5 '17 at 7:36
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    \$\begingroup\$ @Nexy_sm even if there's a net DC current, the AC current to produce the actual signalling transitions would be fairly symmetric since the lines are changing in opposition, and that is largely the most important. \$\endgroup\$ – Chris Stratton May 5 '17 at 17:25
  • \$\begingroup\$ @Nexy_sm, every signaling over a pair of wires has two parameters - differential voltage swing, and common mode voltage. So different can be the terminations - differential termination, and common-mode termination. Ground currents depend on the way how the lines are terminated. The differential signaling can be balanced, or can be unbalanced, edn.com/design/analog/4335533/Understanding-common-mode-signals . Yes, USB uses unbalanced differential signaling, but it is still differential.. \$\endgroup\$ – Ale..chenski May 5 '17 at 17:41
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    \$\begingroup\$ @SimonRichter, yes, there is a state of SE0 - Single Ended Zero, although it is not called "symbol", just EOP - End Of Packet. Every LS/FS packet ends with this state. However, the state with both D+ and D- high is strictly illegal in the USB framework. Therefore the relatively infrequent occurrence of both Dp/Dm at zero doesn't contradict the general spirit of my answer. Yes, USB signaling schema is somewhat eclectic, no argument here. \$\endgroup\$ – Ale..chenski Jul 8 '17 at 17:57
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Common Mode voltage refers to both the AC and DC mean voltage "common to both" conductors.

The DC mean voltage is obvious when you see the levels, but of greater significance is the use of CML or current mode logic at high speeds where instead of using a voltage source with an RdsOn of 25 Ohms or so, it uses a current source switched between outputs that creates a voltage in the terminators on the bus, so that it is matched to the cable impedance and gives the best immunity from RF noise and lowest emissions of the RF signals.

CML is an offshoot improvement in CMOS from the bipolar days of ECL where differential current lines were used for > 1GHz speeds.

CML is not specifically mentioned in the spec, and there may some specific differences, but conceptually it is identical.

Learning the significance of CMRR on cables and differential impedance as well CM impedance differences are key to understanding how high error rates are achieved with wide eye-patterns from cable non-linearities. (kinks etc) and why 3m is the max length for USB3.

...but that's an inference to a deeper question.

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