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I'm looking to design or find a high-side current limiter which can operate at 9V and has ability to limit current to a level of 1,5A with a maximum voltage drop of 1V - 1,2V. It should also be able to survive and limit the current when a short-circuit occures in the load.

When it comes to designing a circuit of my own, best option this far is circuits similiar to

http://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2015/02/IFD2634_F2-big.gif

These circuits typically employ MOSFET and a small current-sense resistor with its signal amplified by an OP.

I'm looking for recommendations and advice on selection of IC/design of a circuit as described above.

P.S

A follow-up question is: With proper, high Vgs and 1,5A of circuit flowing through, how large of a current drop can I expect in a typical MOSFET?

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  • \$\begingroup\$ What is your non-followup question? You should either add you schematic and explain what problems you have or try that provided circuit and ask how to circumvent its limitations. Your followup question can be answered by looking into the datasheet of MOSFETs. The \$ R_{DS(on)} \$ and related graphs are of interest. \$\endgroup\$ May 5, 2017 at 10:03
  • \$\begingroup\$ 9 volts sounds suspiciously like a 9-volt battery. Is this what you are planning to use, and if so do you really think you'll get 1.5 amps out of it? \$\endgroup\$ May 5, 2017 at 11:41
  • \$\begingroup\$ It's not a 9V battery. \$\endgroup\$ May 5, 2017 at 12:43

2 Answers 2

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Start with your requirements and do the math.

Let's think about a current sense resistor followed by a P channel FET. Your maximum voltage budget is 1.2 V at 1.5 A. Let's say the FET can go down to 50 mΩ when fully on. At 1.5 A, that means it will drop 75 mV. That leaves 1.13 V for the resistor. (1.13 V)/(1.5 A) = 750 mΩ. Now you use the voltage across this current sense resistor to control the FET gate. Something like this:

IC2 makes 1.2 V down from the supply voltage. This is scaled by R3 and R4 to the maximum voltage you ever want across the current sense resistor, R1. C2 filters out noise on this scaled reference voltage. IC1A controls the FET gate to attempt to keep the reference voltage across R1. When the load isn't drawing the full current, the opamp output will go as low as it can, turning on the FET fully. When the load draws more current, more voltage builds up across R1. When this exceeds the reference voltage, the opamp output will go high. This turns off the FET, reducing current to the load.

When the load tries to draw more current than the set point, the opamp will regulate the FET gate voltage so that the current is limited right at the set point.

C1 may be needed for stability, depending on the opamp and the FET transfer function. Put the pads there, then experiment with real parts. Find the capacitance where it's just stable and double it. If you don't care about response speed, you can be more conservative and make C1 larger. It might be from a few pF up to 100 pF or so.

The opamp must be chosen carefully. It must be able to run from 9 V, with its input range extending close to the positive supply.

The FET must be able to turn on fully with only 9 V gate drive, minus the opamp output headroom on the low side. At this low voltage, that will be no problem to find. However, you have to look at this and can't just plunk in a random P channel FET that is only specified for 10 or 12 V gate drive.

Power dissipation is another criterion for picking the FET. The worst case is when the load is a short. The current will be regulated to 1.5 A. R1 will drop 1.13 V, so the voltage across the FET will be 7.9 V. That times the current is 12 W. That will definitely require a heat sink.

R1 will dissipate up to 1.7 W. That means it needs to be a "2 W" resistor at minimum. A 5 W resistor would give you better margin and can then be mounted on the board normally.

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  • \$\begingroup\$ One question: when power is dissipated in the load and there is a voltage drop over it, how can I keep Vgs to a high value? It seems to me that this solution would glide into a region where MOSFET has much resistance. \$\endgroup\$ May 5, 2017 at 13:44
  • \$\begingroup\$ @Noob: Yes. The feedback system will adjust the FET as needed to adjust the current. Think of the FET as a variable resistor in series with the load. The opamp is constantly adjusting this resistor to keep the current at 1.5 A. When the current is less than that, it slams the resistor to the minimum. When regulating the current at 1.5 A, it adjusts the resistor to whatever is needed to maintain the 1.5 A. \$\endgroup\$ May 5, 2017 at 13:52
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I looked at your internet circuit. Yes, it could work but it is not cost effective in a modern age. P-channel devices were unobtainium 30 years ago. The photovoltaic stack optocoupler has not got cheaper in 25 years and has reliability issues. So a P-channel design would be cheaper, simpler, and use less space. Your total power wasted under a short circuit is still 13.5 watts with a simple linear circuit. This means a heatsink or some form of thermal management is needed. If your P-channel device has a on resistance of say 100 milliohms, which will not be expensive, it would waste 150mV at 1.5 Amps. The diff amp is not needed if accuracy is not important. Transistor VBE sensing with say 400 milliohms would give about 1.5 Amps. In this simple case about 750mV would be lost at 1.5 Amps.

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