I simulated a miller integrator circuit on multisim online. When I did so I made sure that dc offset in the op amp and the source is zero and also bias and offset currents are zero. But in output to a sine signal (ac) input, the output cosine signal has a negative dc offset. What is causing this offset? Here is the circuit simulated:
There's no offset. It works exactly as it should work. Your integrator charges at the positive half cycle of your V1 and discharges back at the negative half cycle. this is the ideal operation.
In practice the integrator drifts due the leakage currents or opamp offset voltage. It can get stucked to max or min output voltage limit or it can gradually forget the starting point and operate as you probably waited. (= zero average due the leak resistance over the capacitor)
In practical integrator circuits there exists a reset switch or an inserted resistance in parallel with C1.
ADDENDUM: Imagine you have a full glass of water. Take a straw and start to soak. The surface of the water sinks. Spit every drop back. The surface returns exactly to its initial position if you do not add anything of your own and do not forget to spit something back. That's a hydromechanical equivalent process for the behaviour of your circuit.