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Project: LCD initialize on Altera DEO (EP3C16F484C6 FPGA) using Hitachi HD47780

Design: State machine to step through all the necessary timing constraints.

Sources: Based heavily on http://www.xess.com/static/media/projects/LCD_HD44780.pdf

Problem: State outputs are being latched and/or being stuck at Vcc.

Warning (10240): Verilog HDL Always Construct warning at LCD_SM.v(99): inferring latch(es) for variable "EN", which holds its previous value in one or more paths through the always construct

Warning (14026): LATCH primitive "LCD_SM:SM_DUT|EN" is permanently enabled

Trouble Shooting I've Done: I've done some extensive searching through the RTL. According to it, all states and transitions have been inferred correctly. I'm at a loss.

Code:

Top Level

module LCD(LCD_DATA,LCD_RW,LCD_EN,LCD_RS,CLOCK_50,BUTTON);

    input [2:0] BUTTON;
    input CLOCK_50;
    output LCD_EN,LCD_RS,LCD_RW;
    output [7:0] LCD_DATA;

    wire [11:0] i0,i1,i2,i3,i4,i5,i6,i7;
    wire [11:0] i8,i9,i10,i11,i12,i13,i14;
    wire [11:0] i15,i16,i17,i18,i19,i20,i21,i22;

    wire But0;

    wire [4:0] s;

    wire [11:0] y;

    wire Clock, Reset, Delay45ms, Delay80ns, Delay240ns, Delay_TO;
    wire FinalWrite,FirstWrite;

    wire Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us;
    wire CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us;
    wire EN;

    wire [4:0] Inst_Cnt32;

    assign s = Inst_Cnt32;
    assign LCD_DATA = y[7:0];
    assign LCD_RS = y[8];
    assign LCD_RW = 1'b0;
    assign LCD_EN = EN;
    assign Clock = CLOCK_50;
    assign But0 = ~BUTTON[0];
    assign Reset = But0;

    assign i0 = 12'h038;
    assign i1 = 12'h038;
    assign i2 = 12'h038;
    assign i3 = 12'h038;
    assign i4 = 12'h00F;
    assign i5 = 12'h001;
    assign i6 = 12'h006;
    assign i7 = 12'h145;
    assign i8 = 12'h158;
    assign i9 = 12'h154;
    assign i10 = 12'h152;
    assign i11 = 12'h141;
    assign i12 = 12'h120;
    assign i13 = 12'h143;
    assign i14 = 12'h152;
    assign i15 = 12'h145;
    assign i16 = 12'h144;
    assign i17 = 12'h149;
    assign i18 = 12'h154;
    assign i19 = 12'h120;
    assign i20 = 12'h150;
    assign i21 = 12'h14C;
    assign i22 = 12'h15A;

    /*
    module LCD_Datapath(CE240ns,CE80ns,CE45ms,CE32,
                              CE4ms,CE2ms,CE40us,CE100us,
                              Clock,
                              Delay45ms,Delay80ns,Delay240ns,Inst_Cnt32,Delay_TO,
                              Reset45ms,Reset80ns,Reset240ns,ResetPC,
                              Reset4ms,Reset2ms,Reset40us,Reset100us,
                              FinalWrite);
    */

    LCD_Datapath Datapath_DUT(CE240ns,CE80ns,CE45ms,CE32,
                              CE4ms,CE2ms,CE40us,CE100us,
                              Clock,
                              Delay45ms,Delay80ns,Delay240ns,Inst_Cnt32,Delay_TO,
                              Reset45ms,Reset80ns,Reset240ns,ResetPC,
                              Reset4ms,Reset2ms,Reset40us,Reset100us,
                              FinalWrite,
                              FirstWrite);


    /*
    module LCD_SM(Clock,Reset,
                      Delay45ms,Delay80ns,Delay240ns,Delay_TO,Inst_Cnt32,FinalWrite,
                      Reset4ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,
                      Reset40us,Reset100us,
                      CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us);
    */

    LCD_SM SM_DUT(Clock,Reset,
                      Delay45ms,Delay80ns,Delay240ns,Delay_TO,Inst_Cnt32,FinalWrite,
                      Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,
                      Reset40us,Reset100us,
                      CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite);


    /*
    module Mux_9_bit_32_to_1_behavorial(i0,i1,i2,i3,i4,i5,i6,i7,
                                                 i8,i9,i10,i11,i12,i13,i14,
                                                 i15,i16,i17,i18,i19,i20,i21,
                                                 i22,i23,i24,i25,i26,i27,i28,
                                                 i29,i30,i31,
                                                 y,
                                                 s);
    */

    Mux_9_bit_32_to_1_behavorial MUX_DUT(i0,i1,i2,i3,i4,i5,i6,i7,
                                                 i8,i9,i10,i11,i12,i13,i14,
                                                 i15,i16,i17,i18,i19,i20,i21,
                                                 i22,i23,i24,i25,i26,i27,i28,
                                                 i29,i30,i31,
                                                 y,
                                                 s);


endmodule


module LCD_SM(Clock,Reset,
                  Delay45ms,Delay80ns,Delay240ns,Delay_TO,Inst_Cnt32,FinalWrite,
                  Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,
                  Reset40us,Reset100us,
                  CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,
                  EN,
                  FirstWrite);

    input Clock, Reset, Delay45ms, Delay80ns, Delay240ns, Delay_TO;
    input [4:0] Inst_Cnt32;
    input FinalWrite;

    output reg Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us;
    output reg CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us;
    output reg EN;
    output reg FirstWrite;

    parameter Pwr_Up = 4'b0000;
    parameter Pwr_Up_Delay = 4'b0001;
    parameter Off_Pwr_Up_Delay = 4'b0010;
    parameter Write_Data = 4'b0011;
    parameter Data_Setup_Delay = 4'b0100;
    parameter E_Pulse_Hi = 4'b0101;
    parameter E_Hi_Time = 4'b0110;
    parameter E_Pulse_Lo = 4'b0111;
    parameter Proc_Comp_Delay = 4'b1000;
    parameter Load_Next_Data = 4'b1001;
    parameter End0 = 4'b1010;
    parameter End1 = 4'b1011;
    parameter End2 = 4'b1100;
    parameter End3 = 4'b1101;
    parameter End4 = 4'b1110;
    parameter End5 = 4'b1111;

    reg [3:0] state, next_state;

    always@(posedge Clock or posedge Reset)
        begin
            if(Reset)
                state <= Pwr_Up;
            else
                state <= next_state;
        end

    always@(state or Delay45ms or Delay80ns or Delay240ns or Delay_TO or FinalWrite) //need to add transition signals to go with state
        begin
            case(state)

                default: next_state <= Pwr_Up;

                Pwr_Up: next_state <= Pwr_Up_Delay;

                Pwr_Up_Delay: if (Delay45ms)
                                    next_state <= Off_Pwr_Up_Delay;
                                else 
                                    next_state <= Pwr_Up_Delay;

                Off_Pwr_Up_Delay: next_state <= Write_Data;

                Write_Data: next_state <= Data_Setup_Delay;

                Data_Setup_Delay: if(Delay80ns)
                                            next_state <= E_Pulse_Hi;
                                        else 
                                            next_state <= Data_Setup_Delay;

                E_Pulse_Hi: next_state <= E_Hi_Time;

                E_Hi_Time: if(Delay240ns)
                                next_state <= E_Pulse_Lo;
                            else 
                                next_state <= E_Hi_Time;

                E_Pulse_Lo: next_state <= Proc_Comp_Delay;

                Proc_Comp_Delay: if(Delay_TO)
                                        next_state <= Load_Next_Data;
                                    else 
                                        next_state <= Proc_Comp_Delay;

                Load_Next_Data: if(FinalWrite)
                                        next_state <= End0;
                                    else 
                                        next_state <= Write_Data;

                End0: next_state <= End1;

                End1: next_state <= End2;

                End2: next_state <= End3;

                End3: next_state <= End4;

                End4: next_state <= End5;

            endcase
        end

    always@(state)
        begin
            case(state)

                default:          {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b111111110000000000;

                Pwr_Up:              {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b111111110000000000;

                Pwr_Up_Delay:     {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b111111110000000000;

                Off_Pwr_Up_Delay: {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b111111110000000000;

                Write_Data:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;

                Data_Setup_Delay: {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000100000000;

                E_Pulse_Hi:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000001000000010;

                E_Hi_Time:        {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000001000000010;

                Proc_Comp_Delay:
                    begin
                            if (Inst_Cnt32 == 0)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000001;
                                end
                            else if (Inst_Cnt32 == 1)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000100000;
                                end
                            else if (Inst_Cnt32 == 2)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000100;
                                end
                            else if (Inst_Cnt32 == 3)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 4)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 5)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 6)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000010000;
                                end
                            else if (Inst_Cnt32 == 7)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 8)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 9)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 10)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 11)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 12)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 13)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 14)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 15)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 16)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 17)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 18)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 19)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 20)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 21)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 22)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 23)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 24)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 25)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 26)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 27)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 28)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 29)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 30)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 31)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                            else if (Inst_Cnt32 == 32)
                                begin
                                    {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000001000;
                                end
                    end

                Load_Next_Data: {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b011000100001000000;

                End0:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;

                End1:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;

                End2:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;

                End3:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;

                End4:       {Reset45ms,Reset80ns,Reset240ns,ResetPC,Reset4ms,Reset2ms,Reset40us,Reset100us,CE240ns,CE80ns,CE45ms,CE32,CE4ms,CE2ms,CE40us,CE100us,EN,FirstWrite} <= 18'b000000000000000000;


            endcase
        end

endmodule

module LCD_Datapath(CE240ns,CE80ns,CE45ms,CE32,
                          CE4ms,CE2ms,CE40us,CE100us,
                          Clock,
                          Delay45ms,Delay80ns,Delay240ns,Inst_Cnt32,Delay_TO,
                          Reset45ms,Reset80ns,Reset240ns,ResetPC,
                          Reset4ms,Reset2ms,Reset40us,Reset100us,
                          FinalWrite,
                          FirstWrite);

    input Clock;
    input Reset45ms,Reset80ns,Reset240ns,ResetPC;
    input Reset4ms,Reset2ms,Reset40us,Reset100us;
    input CE240ns,CE80ns,CE45ms,CE32;
    input CE4ms,CE2ms,CE40us,CE100us;
    input FirstWrite;

    output [4:0] Inst_Cnt32;
    output Delay45ms,Delay80ns,Delay240ns,Delay_TO;
    output FinalWrite;

    wire [4:0] Eighty_ns,TwoForty_ns;
    wire [21:0] FortyFive_ms,Four_ms,Two_ms,Forty_us,Hundred_us;
    wire Delay4ms,Delay2ms,Delay40us,Delay100us;
    wire FirstWrite;

    assign Delay_TO = Delay4ms|Delay2ms|Delay40us|Delay100us|FirstWrite;

    //module Counter_22bit(Clock,Reset,CE,Counter);
    Counter_22bit FortyFiveMilSec(Clock,Reset45ms,CE45ms,FortyFive_ms),
                      FourMilSec(Clock,Reset4ms,CE4ms,Four_ms),
                      TwoMilSec(Clock,Reset2ms,CE2ms,Two_ms),
                      FortyMicSec(Clock,Reset40us,CE40us,Forty_us),
                      HundredMicSec(Clock,Reset100us,CE100us,Hundred_us);


    //module Counter_5bit(Clock,Reset,CE,Counter);
    Counter_5bit EightyNanSec(Clock,Reset80ns,CE80ns,Eighty_ns),
                     TwoFourtyNanSec(Clock,Reset240ns,CE240ns,TwoForty_ns),
                     WriteCounter(Clock,ResetPC,CE32,Inst_Cnt32);

    //module comparator_standalone(A,B,G,E,L);
    comparator_5bit FinalWriteCompar(Inst_Cnt32,22,G,FinalWrite,L),
                         Eightyns(Eighty_ns,4,g,Delay80ns,L),
                         TwoFortyns(TwoForty_ns,12,g,Delay240ns,L);                          
    comparator_22bit FortyFivems(FortyFive_ms,2250000,G,Delay45ms,L),
                          Fourms(Four_ms,200000,G,Delay4ms,L),
                          Twoms(Two_ms,100000,G,Delay2ms,L),
                          Fortyus(Forty_us,2000,G,Delay40us,L),
                          Hundredus(Hundred_us,5000,G,Delay100us,L);



endmodule
\$\endgroup\$
1
\$\begingroup\$

You need a final else in that gigantic inst_cnt32 if statement. Btw, that code is impossible to read.

\$\endgroup\$
2
  • \$\begingroup\$ Thank you, I'll check this, and sorry, I will work on that \$\endgroup\$ May 7 '17 at 0:41
  • \$\begingroup\$ It worked, thank you very much. And again, sorry for the bad code. \$\endgroup\$ May 7 '17 at 1:03

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